台积电或抢先英特尔一步推出3-D芯片堆叠产品

据台湾对外贸易发展协会(TAITRA)透露，芯片代工巨头台积电（TSMC）有望超过intel，在2011年底推出业内首款采用3-D芯片堆叠技术的半导体芯片产品。 TAITRA的报告援引了一则匿名消息： Intel曾于今年5月表示，他们将于今年年底前开始量产结合了三门晶体管技术（台积电计划14nm节点启用类似的Finfet技术）的芯片产品。而台积电这次推出采用3-D芯片堆叠技术半导体芯片产品的时间点则与其非常靠近。 虽然台积电在与intel的3-D芯片竞速比赛中获胜了，但需要说明的是，台积电采用的技术与Intel的三门晶体管技术存在很大的区别。台积电开发的3-D芯片堆叠技术与其它半导体厂商一样，以穿硅互联技术（TSV）为核心 ，通过在互联层中采用TSV技术来将各块芯片连接在一起，以达到缩小芯片总占地面积，减小芯片间信号传输距离的目的。而英特尔采用的三门晶体管技术则是从芯片的核心部分晶体管内部结构上进行改革，业界称为FinFET，因为硅通道类似于一个从半导体基片上凸起来的鳍。 根据外贸协会的报告，3-D技术等效增大了单芯片中的晶体管密度高达1000倍，而能耗则可降低50％左右。新技术有望解决传统的“平面”的晶体管遇到的只能二维移动电子的困难。 在增加芯片单位面积内的晶体管密度方面，3-D芯片堆叠技术和三门晶体管技术均能起到正面的影响作用。 TAITRA还引用了台积电研发部门高级副总裁蒋尚义的话称，台积电一直都在与芯片封装商，以及芯片自动化设计软件开发商就改善3-D芯片堆叠技术的实用性方面进行紧密合作。 编译：Luffy Liu 本文授权编译自EE Times， 版权所有，谢绝转载 参考英文原文：Report: TSMC may beat Intel to 3-D chips, by Dylan McGrath

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{pagination} Report: TSMC may beat Intel to 3-D chips Dylan McGrath BATTLE MOUNTAIN, Nev.—Chip foundry giant Taiwan Semiconductor Manufacturing Co. (TSMC) could deliver its first semiconductors with 3-D interconnects by the end of 2011, potentially beating Intel Corp. to the punch in offering the first 3-D chips, according to a report circulated Tuesday (July 5) by a Taiwan trade group. The report by the Taiwan External Trade Development Council (TAITRA) quoted an anonymous source saying that TSMC's projected delivery of 3-D chips matches that of Intel, the world's biggest chip maker. Intel announced with great fanfare in May that it would begin high-volume production of 3-D chips using tri-gate transistors by the end of the year. While the TAITRA report pits TSMC against Intel in a race to produce the first 3-D chips, the technologies at issue are actually quite different. TSMC and others have for some time been developing technology for chips with 3-D interconnect, called through silicon vias (TSVs)--vertical connections that pass through die to connect different layers of a chip within the same package. Intel's tri-gates are actually 3-D transistors, known outside Intel as a FinFets because the silicon channel is akin to a fin jutting up from the semiconductor substrate. According to the TAITRA report, 3-D technology boosts the density of transistors in a single chip by up to 1,000 times. The 3-D devices are also expected to consume about 50 percent less energy. The new technology is expected to override a number of difficulties posed by traditional "planar" transistors, which can only move electrons across two dimensions, according to the report. Shang-Yi Chiang, senior vice president for R&D at TSMC, was quoted in the TAITRA report saying TSMC has been working closely with chip packagers and providers of design auto software to commercialize 3-D chip technology.