台积电：14nm节点延期，都怪设备商不给力

在Semicon Taiwan半导体设备展上，晶圆代工大厂台积电(TSMC)的高层指出，要赶上 14奈米节点芯片在2015年的量产时程，时间已经不多了，但设备业者却动作太慢。台积电认为，要让 14奈米芯片达到成本效益，需要采用下一代微影技术以及 18寸晶圆，但设备业者在这两方面都没有赶上晶圆代工业者的时间表。 台积电研发资深副总蒋尚义(Shang-Yi Chiang)表示：“我们一天比一天更担心。”晶圆厂的产能需要达到每小时100片以上晶圆片，但到目前为止，超紫外光(EUV)微影技术产量最多仅能达到每小时5片晶圆；其它两种采用多重电子束直写方案的备选微影技术，一小时的产量甚至不到1片晶圆。 “台积电在几个月之前就提出了我们的 18寸晶圆愿望清单，但有部分设备业者认为那太赶了，所以现在我们也不知道确切的时间表将会如何；”蒋尚义接受EETimes编辑访问时指出：“我们可能得采取转换至0.13微米制程时的做法，当时有部分产能是采用8寸晶圆，有部分是采用12寸晶圆。” 台积电目前计划在新竹的Fab 12建置一条18寸晶圆试产线，然后在台中设置量产线；更大尺寸的晶圆片将有助于半导体产业赶上摩尔定律(Moore's Law)的脚步，并将IC制造成本降低至少30%。18寸晶圆可让代工业者减少晶圆厂数量，并因此节省大量的土地与人力成本。 举例来说，为了达到3,200万片8寸约当晶圆的产能需求，若以现在的12寸晶圆进行生产，台积电得雇用2万7,000名工程师维持29座厂房营运，但如果采用18寸晶圆，只需要2万名工程师、22座厂房。“18寸晶圆不是一个技术议题，而是一个在这些日子以来比技术更重要的经济议题。”蒋尚义表示。

18寸晶圆可让业者节省土地与人力成本NPFesmc

在微影技术方面，目前的193奈米浸润式微影系统将使用于台积电目前正在量产的28奈米节点，以及下一代的20奈米节点制程；但在20奈米节点部分，晶圆厂会需要用到双重图形(double patterning)方案，基本上就是让晶圆片透过某种程序曝光两次，以画上更细的线条。 而到了14nm节点，以浸润式微影设备做双重图形，对许多客户来说价格会变得非常高，所以台积电将在两周内开始测试ASML的3100系列EUV微影设备原型机；该公司已经开始测试Mapper Lithography的电子束微影设备，并计划在明年装设另一台由KLA Tencor提供的电子束微影设备。 “如果我们无法让EUV或电子束微影设备，达到每小时100片晶圆的产量，我们可能会看到很少有客户愿意继续迈向更精细的制程技术节点，因为成本实在太高。”蒋尚义表示，台积电计划在2015年量产14nm节点制程，所以：“我们必须在明年决定要用哪一种微影设备。如果我们继续专注于采用193奈米浸润式微影，稍后要转换至EUV会变得很困难，而且设计规则必须要根据所选择的微影技术来定义，所以时间真的很赶。”

14奈米制程节点所需的微影技术成本飙高NPFesmc

蒋尚义表示，浸润式微影技术在14奈米节点会变得非常昂贵，颠覆以往每升级一个节点、资本设备支出会减半的原则；而虽然EUV与电子束微影设备的成本也很高，估计至少需要1.2亿美元，但还是会比以浸润式微影技术进行双重图形来得便宜许多。他并指出，电子束与EUV设备的价格差不多，但目前正在进行测试的电子束微影设备不需要光罩，所以成本会比EUV微影技术稍低一些。 编译：Judith Cheng 本文授权编译自EE Times，版权所有，谢绝转载 参考英文原文： TSMC says equipment vendors late for 14 nm，by Rick Merritt

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{pagination} TSMC says equipment vendors late for 14 nm Rick Merritt TAIPEI – Time is running out to make critical decisions for how to make 14-nm chips expected to hit production in 2015, and capital equipment vendors are falling behind. That was the upshot of a talk by the top R&D executive at Taiwan Semiconductor Manufacturing Co. (TSMC) at Semicon Taiwan here. TSMC believes it needs to move to next-generation lithography and 450-mm wafers to make 14-nm chips cost effectively, but capital equipment makers threaten to miss the foundry's schedule on both fronts. "Every day we become more and more concerned," said Shang-Yi Chiang, senior vice president of R&D of TSMC. Fabs need throughput of more than 100 wafers per hour. But so far extreme ultraviolet (EUV) lithography offers just five wafers per hour at best. Two alternatives using multiple e-beam direct write approaches get less than one. Similarly, TSMC "put out our wish list for 450-mm wafers a few months ago, but some in the capital equipment industry felt it was too aggressive so now we don’t know" what the schedule will be, Chiang said to EE Times after his talk. "We may have to do what we did at the 130-nm generation when some capacity was on 200- and some on 300-mm wafers," he said. TSMC currently plans to bring up a pilot 450-mm wafer line at its Fab 12 in Hsinchu, followed by a production line in Taichung. The larger wafers are needed both to help keep pace with Moore's Law and to lower wafer costs as much as 30 percent. The 450-nm wafers enable foundries to use fewer fabs, saving significant money on both land and labor costs. To meet expected demand for 32 million eight-inch equivalent wafers, TSMC could hire 20,000 engineers to run 22 plants. If it has to use today's 300-mm wafers the same output would require 29 plants and 27,000 engineers, Chiang estimated. "450-mm wafers are not a technical issue but an economic issue which is probably more important than technical issue these days," Chiang said. In lithography, today's 193-nm immersion systems will serve both the 28-nm node TSMC is ramping now and the next-generation 20-nm node. But at 20 nm, fabs will need to use double patterning, essentially running wafers through some exposure processes twice to draw finer lines. At 14 nm the amount of double patterning with immersion systems could become prohibitively expensive for many customers. So TSMC will start testing a prototype 3100 series EUV machine from ASML in two weeks. It has already been testing an e-beam system from Mapper Lithography BV and will install another from KLA Tencor next year. "If we cannot get EUV or e-beam to 100 wafers per hour throughput, we see few customers will be willing to continue migrating to finer technology nodes because of the cost," he warned. TSMC hopes to ramp a 14-nm process in 2015 so "we have to make this decision [on lithography] early next year," Chiang said. "If we focus on using 193-nm immersion it becomes difficult to switch to EUV later on, [and] design rules will be defined based on the choice of lithography, so time is running out," he said. New transistors needed at 14nm Chiang suggested immersion lithography would be too expensive at 14 nm, exceeding traditional guidelines of half the capital equipment costs for a node. Despite the enormous costs of EUV and e-beam machines, estimated at as much as $120 million, they are still cheaper than immersion given the double patterning problems. E-beam and EUV systems cost roughly the same. But E-beam systems currently under test do not require masks so could slightly cheaper to use than EUV, Chiang said. EUV has "the broadest support and is the most likely route" forward, said Luc Van den hove, chief executive of the Imec research consortium based outside Brussels. "But this year and next we have to demo the production worthiness of this technology," Van den hove said in a separate talk. Imec has been running wafers through an ASML 3100 pre-production system for three months "and we've seen improvement in throughput, but progress has been too slow and we have to further accelerate it," he said. The power of the EUV source light is still too low, despite defining two approaches to creating the light source. "Progress has not been sufficient, and this is one of the highest priorities," said Van den hove who once ran Imec's lithography program. As if the capital equipment problems were not enough, TSMC expects it will need to transition to a new transistor design at 14 nm, likely a FinFET. Intel announced plans to use such a 3-D transistor design starting at 20 nm. Both TSMC and GlobalFoundries believe planar transistors can be used down to 20 nm. But they both expect to make the switch to 3-D structures such as FinFETs or fully depleted SOI at 14 nm. Van den hove said FinFETs "are probably the most likely way. Beyond that we believe another technology breakthrough will be needed likely using super-high mobility materials such as germanium p-channel and III-IV materials for n-channels for 10 nm nodes," he added. The good news is unexpected innovations have powered the industry past roadblocks in previous generations, despite as many as ten past predictions that Moore's law would end, said Chiang of TSMC. Based on feasibility demonstrations, he projected currently defined technologies could take CMOS scaling to geometries as fine as 7 nm.