半导体制程再微缩下去，还有经济效益吗？

晶圆代工大厂台积电(TSMC)资深研发副总裁蒋尚义(Shang-Yi Chiang)在日前于美国举行的ARM技术论坛(TechCon)上表示，在接下来十年以FinFET技术持续进行半导体制程微缩的途径是清晰可见的，可直达 7nm节点；但在 7nm节点以下，半导体制程微缩的最大挑战来自于经济，并非技术。 蒋尚义表示，他有信心半导体产业将在接下来十年找到克服7nm以下节点技术障碍的解决方案；但也指出，新技术虽然能实现7nm以下节点制程芯片量产，却可能得付出高昂代价：“当制程节点演进，我们也看到晶圆制造价格比前一代制程增加了许多。”

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在ARM技术论坛的另一场专题演说中，EDA供货商Cadence Design Systems旗下Silicon Realization部门的资深研发副总裁徐季平(Chi-Ping Hsu)，演示文稿了半导体制程从32/28nm节点过渡到22/20nm节点的制程技术研发成本增加幅度；他举例指出，如果32/28nm节点需成本是12亿美元，来到22/20nm节点，该成本规模将增加至21至30亿美元。 至于芯片设计成本，则会从32nm节点所需的5,000万至9,000万美元，在22nm节点增加至1.2亿至5亿美元。徐季平并指出，在32nm节点，芯片销售量需要达到3,000至4,000万颗，才能打平成本；但到了20nm节点，该门槛会提高至6,000万至1亿颗。

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FinFET是一种 3D晶体管技术，目前正初步获得芯片制造商的采用；大厂英特尔(Intel)则是将其3D晶体管技术称为“三闸(tri-gate)”，业界预计该公司将在今年底推出采用3D晶体管技术所生产的22nm芯片样品。 蒋尚义表示，22nm节点会是半导体产业采用平面晶体管技术(planar transistor)的最后一个时代：“在此之后，该技术就会功成身退。” 编译：Judith Cheng 本文授权编译自EE Times，版权所有，谢绝转载 参考英文原文：TSMC's R&D chief sees 10 years of scaling，by Dylan McGrath

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{pagination} TSMC's R&D chief sees 10 years of scaling DylanMcGrath SANTA CLARA, Calif.—The path is clear for continued semiconductor scaling using FinFETs for the next decade, down to the 7-nm node, according to Shang-Yi Chiang, senior vice president of R&D at foundry giant Taiwan Semiconductor Manufacturing Co. Beyond 7-nm, the most pressing challenges to continued scaling will come from economics, not technology, Chiang said in a keynote address at the ARM TechCon event here Tuesday (Oct. 25). Chiang (above) said he has faith that the semiconductor industry will solve technical hurdles associated with moving past 7-nm over the next decade, but acknowledged that the new technologies might make volume manufacturing of chips with critical dimensions smaller than 7-nm cost prohibitive. "From node to node, we have found the wafer price has increased much more than previous nodes," Chiang said. In another ARM TechCon keynote later, Chi-Ping Hsu (right), senior vice president of R&D at in EDA vendor Cadence Design Systems Inc.'s Silicon Realization Group, presented data on dramatic cost increases associated with moving from the 32/28-nm node to the 22/20-nm node. The amount of money invested by the semiconductor industry in process R&D, for instance, jumped from $1.2 billion at 32/28 to between $2.1 billion and $3 billion at 22/20, Hsu said. Design costs for a chip jump from $50 million to $90 million at 32-nm to $120 million to $500 million at 22-nm, Hsu said. At the 32-nm node, a chip needs to sell about 30 to 40 million units to recoup the costs associated with it, Hsu said. At the 20-nm node, the "breakeven" point jumps to between 60 and 100 million units, Hsu said. FinFETs are three-dimensional transistors in the early stages of being adopted by chip makers. Intel Corp., which refers to its 3-D transistor technology as "tri-gate," is expected to begin sampling 22-nm chips with 3-D transistors later this year. Chiang said the 20-nm node will be the last generation at which the semiconductor industry can possibly use a planar transistor. "After that, it will run out of steam," Chiang said.