PCIe接口将进入智能手机和平板电脑

作为PC和 服务器的I/O骨干技术， PCI Express (PCIe) 最近积极朝低功耗领域扩展，预计明年起将Ultrabook 、平板电脑(tablets)和智能手机都纳入目标市场。这种强化的互连技术据称能让移动装置在连接到高性能外围，如 60GHz 无线网络控制器和固态硬盘(SSD)时，降低两倍到四倍的功耗。 PCI特别任务小组(PCI Special Interest Group)希望今年底前能通过针对 PCIe 3.0 底层软件的新版规范。该程序代码将执行在由 MIPI 联盟(MIPI Alliance)定义的M-PHY实体层芯片上，为移动装置提供全新接口。 这两大组织已于上周一(九月十日)签署协议。PCI SIG将开发针对M-PHY的下一代PCIe 4.0软件。 “低功耗版本的PCI Express一直是我们追求的目标，因为我们都知道，真正大量的消费者和大量的需求在哪里，”PCI SIG主席 Al Yanes说。 特别的是，PCI SIG将会定义其实体链接层软件的变种，以便能执行在M-PHY上。其程序代码将可实现多个非对称信道、动态频宽协调，并大幅降低电磁干扰。 “我们设计让移动装置更容易导入 PCI Express，”MIPI联盟副主席Brian Carlson说。 去夫，一位资深的 Marvell 公司工程经理表示，希望用行动互连来将他的应用处理器连接到一个外部的 802.11ac 控制器。该连接必须能在1.8V供给电压下达到1.1Gb/s速率、少于38milliwatts的功耗。 新的M-PHY结合了PCI Express，能满足上述需求，Carlson说。在2011年4月定义的M-PHY速率为1.25Gb/s，而2012年6月公布的新版本速率则达到2.9Gb/s；预计明年发布的第三版还将推升到5.8Gb/s。 该连接在铜线上支持30公分，在光缆上支持5公尺距离。PCIe 3.0本身支持高达8 GTransfers/second速度。 2012年，预估将有超过30亿个采用MIPI接口的装置出货，Carlson说。其中许多使用较旧型的D-PHY链接，执行速度约500Mb/s，通常用于移动显示器和相机等。 而新的PCIe over M-PHY则能满足动态功耗、最大能量消耗等需求。PCI SIG今年6月针对PCIe 3.0发布新规范也满足了英特尔在新一代处理器 Haswell 中纳入的新闲置功耗技术要求。 本文授权编译自EE Times，版权所有，谢绝转载 编译： Joy Teng 参考英文原文：Smartphone is next stop for PCI Express，by Rick Merritt

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{pagination} Smartphone is next stop for PCI Express Rick Merritt SAN FRANCISCO -- PCI Express, the I/O backbone of PCs and servers, is getting a low-power extension that will take it into Ultrabooks, tablets and smartphones starting next year. The enhanced interconnect will draw two to four times less power while helping mobile devices link to high-performance peripherals such as 60-GHz wireless networking controllers and solid-state drives. The PCI Special Interest Group expects to approve by the end of the year a new version of its low level software for PCIe 3.0. The code will run on the M-PHY physical layer chips defined by the MIPI Alliance that creates handset interfaces. The two groups signed a deal Monday (Sept. 10), cementing their collaboration. The PCI SIG will also create a version of its next-generation PCIe 4.0 software for M-PHY. “We’ve been chasing for months the Holy Grail of getting to a lower power version of PCI Express because we know that’s where the volume is and where the users are,” said Al Yanes, chairman of the PCI SIG. Specifically, the PCI SIG will define a new variant of its physical link layer software to run the M-PHY. The code will enable multiple asymmetrical lanes, dynamic bandwidth negotiation and lower electromagnetic interference. “We are making PCI Express mobile friendly,” said Brian Carlson, vice chairman of the MIPI Alliance. Last year, a senior Marvell engineering manager called for a mobile interconnect to link his applications processor to an external 802.11ac controller. The link needs to deliver 1.1Gbits/s while consuming less than 38 milliwatts on a 1.8-volt supply, he said. The new M-PHY combined with PCI Express addresses that need, said Carlson. M-PHY was first defined in April 2011 at 1.25 Gbits/s, an update released in June 2012 runs at 2.9 Gbits/s and a third generation coming next year will hit up to 5.8 Gbits/s. The link is defined over copper traces at up to 30 cm and over optical lengths up to five meters. For its part, PCIe 3.0 supports up to 8 GTranfers/second. As many as three billion devices using MIPI interfaces could ship in 2012, said Carlson. Many of them use an older D-PHY link, running at about 500 Mbits/s, geared for mobile displays and cameras. The new variant of PCIe over M-PHY addresses active power, the biggest consumer of energy. The PCI SIG released in June an addition to its PCIe 3.0 spec addressing idle power, a technology Intel incorporated into the design of its next-generation processor, Haswell.