三星一马当先，将在ISSCC展示big.little处理器

三星(Samsung)将在明年二月的国际固态电路大会(ISSCC)中，展示采用 ARM big.little 概念的移动应用处理器。 这是少数将在该会议大披露的新款微处理器，但包括英特尔(Intel)的 Haswell 和 Nvidia 的丹佛计划(Project Denver)，都很明显地缺席。不过，英特尔和 Nvidia 都将就新的芯片到芯片连接提出最新论文，展示他们对未来处理器的规划。 三星将揭露具有两个四核心丛集的 28nm SoC 详细资料。其中一个丛集执行在1.8GHz，具有2MB L2 快取，主要针对高性能应用；另一款速度为1.2GHz，可用于调节能源效率。 该芯片与 ARM 所提出之采用 32位 A15 和 A7 核心的 big.little 架构相同。今年10月时，ARM曾表示这种方法提供了比预期还要高的效益，未来将广泛应用在智能手机中。 Linley Group 资深分析师Kevin Krewell表示，三星将推出首款 big.little 处理器。 A7 核心应该能处理大多数智能手机的任务，而A15核心则处理需要高性能的需求，如游戏。 而其它如高通(Qualcomm)、 Nvidia 和其它预计2013年推出，将与英特尔 22nm Haswell 在平板市场竞争的处理器则并未计划在 ISSCC 上披露。根据过去经验，英特尔在会议上提出的论文向来与处理器无关。 不过，这家 x86 巨擘将描述一款频宽达1Tb的可扩展64信道芯片到芯片互连。 该链路使用多个2~16Gb/s信道，执行在0.8~2.6 pJ /bit，采用32nm CMOS制程，总总线功耗为2.6W 这篇文章介绍了英特尔研究院(Intel Labs)的研究成果。英特尔实验室资深首席工程师Bryan Casper表示，该论文描述了使用Samtec的micro-twinax线路，以及 Ardent Concepts 的连接器来连接Tb/s等级的芯片，否则功耗可能会拉升至20W。 Casper表示，直径1到2mm的线束将是“我们在跨越移动和 服务器应用时，向前迈进的重要技术。次pJ /bit I/O非常重要，因为这是快速开启和关闭I/O连接的关键。” Nvidia将描述一款20Gb/s的串行芯片到芯片28nm CMOS，它采用0.9V电源，电源效率0.54pJ/b。这项互连技术可能会与Nvidia的丹佛计划整合，也可能应用在从笔电到超级计算机等所有ARM和绘图核心处理器系列中。 此外，中国科学院计算技术研究所(ICT)将提出新版龙芯3B处理器 (Godson 3B)，该组件采用32nm。在此之前，ICT展示过八核心65nm CPU，并建议直接跨越到32nm。 在 ISSCC上，工程师将详细介绍Godson-3B1500，这是一款32nm high-K金属闸极组件，在1.35 GHz、40W条件下可提供172.8 GFLOPS性能。在同等功耗条件下，新处理器性能较65nm版本的128 Gflops有显著提升，这主要归功于新制、架构和电路的改良。 在其它论文中，德州仪器(TI)和麻省理工学院(MIT)将提出一款200MHz的影像译码器，可符合高效影像编码标准，提供每秒249M画素性能。它支持3,840 × 2,160画素分辨率，在0.9V时耗电76mW。 瑞萨(Renesas)将描述一款整合手机芯片，其中包含28nm双核心1.5GHz CPU、 LTE/HSPA + 基频调制解调器处理器、绘图加速器和电源管理单元。 AMD, IBM和甲骨文(Oracle)则将分别就其 Jaguar, zSeries 和 Sparc T5 发表论文。 本文授权编译自EE Times，版权所有，谢绝转载 编译： Joy Teng 参考英文原文：ISSCC: Samsung big.little, but no Intel, Nvidia CPUs，by Rick Merritt

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{pagination} ISSCC: Samsung big.little, but no Intel, Nvidia CPUs Rick Merritt SAN JOSE, Calif. – Samsung will describe the first mobile applications processor to use ARM’s big.little concept at the International Solid-State Circuits Conference in February. That's one of only a few major new microprocessor disclosures at the semiconductor industry's premier conference where Intel’s Haswell and Nvidia’s Project Denver parts are noticeably absent. However, both Intel and Nvidia will deliver papers on new chip-to-chip links that may provide an oblique view on their future processor plans. Samsung will detail a 28-nm SoC with two quad-core clusters. One cluster runs at 1. 8 GHz, has a 2 MByte L2 cache and is geared for high performance apps; the other runs at 1.2 GHz and is tuned for energy efficiency. The chip clearly parallel’s ARM’s description of a big.little architecture using its 32-bit A15 and A7 cores. In October, ARM said the approach is delivering greater than expected benefits and expects it will become widely used in smartphones. “We expect the Samsung part is the first big.little processor,” said Kevin Krewell, senior analyst with market watcher Linley Group (Mountain View, Calif.). “The A7 cores should be capable of handling most [smartphone] tasks, with the A15 cores only required for maximum performance needs, like video games,” he said. The chip and ones like it from Qualcomm, Nvidia and others will roll out in 2013, competing for sockets in tablets with Intel’s 22-nm Haswell, which will not be described at ISSCC. In a departure from past years, Intel will present no processor papers at the event. However, the x86 giant will describe a scalable 64-lane chip-to-chip interconnect with 1 Tbit/s aggregate bandwidth. The link uses multiple 2-16 Gbit/s channels running at power efficiencies of 0.8 to 2.6 pJ/bit in 32nm CMOS with a total bus-level power consumption of 2.6 W. The paper describes research at Intel Labs that is not necessarily related to a clustering interconnect the company announced in September for future x86 and Atom server processors. It describes research using so-called micro-twinax wiring from Samtec, and connectors from Ardent Concepts to link chips at Tbit/s rates that otherwise might draw up to 20 W, according to co-author Bryan Casper, a senior principal engineer overseeing I/O research at Intel Labs. The 1 to 2 millimeter diameter wire bundles will be “a very important technology for us going forward for some segments” spanning mobile and server apps, said Casper. “Sub picojoule per bit I/O is really important, as are fast on and off I/O links." Separately, NVidia will describe a 20 Gbit/s serial die-to-die link made in 28-nm CMOS. It runs on a 0.9 V supply and has power efficiency of 0.54pJ/b. The interconnect might be part of Nvidia’s Project Denver, a still secretive family of processors merging ARM and graphics cores for everything from notebooks to supercomputers. Godson update “It could be part of Project Denver or a technology to connect multiple GPUs together for Tesla-based supercomputer support,” said Krewell of Linley Group. “I haven't heard any details of how Project Denver is proceeding, but Nvidia certainly needs to develop high performance interfaces that can connect arrays of Project Denver heterogeneous processors." Nvidia’s graphics chips are already widely used in massive clusters for supercomputers, including the world’s current fastest system called Titan. Separately, China’s Institute of Computing Technology will describe a new version of the Godson 3B processor made using a 32-nm process. Previously ICT showed eight-core 65-nm CPUs and suggested it would leapfrog to 28-nm designs. At ISSCC, engineers will detail Godson-3B1500, a 32-nm high-K, metal gate part delivering 172.8 Gflops when running at 1.35 GHz at 40 W. That’s up from 128 Gflops for the 65-nm version also drawing 40 W, thanks to the new process as well as architecture and circuit enhancements. Among other papers, Texas Instruments and MIT will describe a 200-MHz video decoder implementing the High-Efficiency Video Coding draft standard to deliver 249 Mpixels/s. It enables 3840 x 2160 pixel resolution while consuming 76 mW at 0.9 V. Renesas will describe a 28-nm integrated handset SoC with a dual-core 1.5 GHz CPU, an LTE/HSPA+ baseband modem processor, graphics accelerators and a power management unit. AMD, IBM and Oracle will present papers on their Jaguar, zSeries and Sparc T5 processors already described in August at Hot Chips.