专门针对智能手机与平板设备应用的移动版 PCI Express (PCIe)互连接口规格已经出炉，在日前于美国举行的一场 PCI 工作小组(Special Interest Group，SIG)年度会议上，EDA供货商Cadence与Synopsys都展示了该种 M-PCIe 规格的工作芯片。
新规格将PCIe通信协议搭载于产业组织 MIPI 所定义的、已经广泛应用于移动设备的M-PHY之上，可协助设备制造商藉由重复利用PCIe软件来降低成本、缩短开发时间，并可取代目前市面上各种各样的行动装置互连协议。
M-PCIe 是本年度 PCI SIG 年会上的主角，预期未来会在应用处理器、Wi-Fi 组合组件、桥接芯片与储存控制器等芯片上出现；来自Cadnece的一位产品经理表示，首款采用该规格的系统单芯片可望在明年初问世。
Cadence展示采用第二代数据传输速率、在2.9GHz频率运作的M-PCIe 芯片
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Synopsys展示采用第三代数据传输速率、在5.8GHz频率运作的M-PCIe 芯片
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本文授权编译自EE Times，版权所有，谢绝转载
本文下一页：M-PCIe规格书只有60页
相关阅读：
• Altera推出业界首款符合5Gbps PCIe Gen2要求的低功耗FPGA
• 移动设备、嵌入式应用前景看好，带动接口IC需求
• 高速通信接口升级引发测试新需求Ojyesmc
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M-PCIe规格书只有60页，与其它PCI SIG旗下的标准规格相较简洁了许多，这是因为该规格大部分是参考现有的MIPI M-PHY与第三代PCI协议规格；M-PCIe旨在做为应用处理器与基频芯片、Wi-Fi组合芯片、储存芯片等的连接接口。
M-PCIe规格大部分是参考现有的MIPI M-PHY与第三代PCI协议
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本文授权编译自EE Times，版权所有，谢绝转载
本文下一页：缆线版PCIe频宽比Thunderbolt更大，成本更低
相关阅读：
• Altera推出业界首款符合5Gbps PCIe Gen2要求的低功耗FPGA
• 移动设备、嵌入式应用前景看好，带动接口IC需求
• 高速通信接口升级引发测试新需求Ojyesmc
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此外， PCI SIG 也预期在2014年6月以前完成32Gbps速率的缆线(cable)版本PCIe规格──OcuLink；PCI SIG行销小组主席Ramin Neshanti表示，该版本规格的频宽比苹果(Apple)与英特尔(Intel)所支持的竞争互连技术Thunderbolt更大，而且成本更低。
PCI SIG 还发表了第四代 PCIe 规格的进展，此版本预期会是该种铜线PCB互连规格的最后一次更动，将支持每秒16 GTransfers传输速率，预计2015年初完成。该工作小组在年会中也介绍了8GT/s速率的第三代PCIe规格功能提升详情，以及针对行动装置应 用、旨在取代mini-PCIe卡的硬件新规格M. 2。
M. 2包含十几种可取代Wi-Fi组合芯片、固态硬盘与其它外围装置应用的Mini PCIe与Half Mini PCIe卡的硬件规格；该规格的0.7版预计在今年底完成。
将取代Mini PCIe卡的M. 2规格
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Oculink规格将未来将支持第四代PCIe与主动光纤电缆，向Thunderbolt 挑战
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本文授权编译自EE Times，版权所有，谢绝转载
本文下一页：第四代PCIe速率16 GT/s，2015年完成
相关阅读：
• Altera推出业界首款符合5Gbps PCIe Gen2要求的低功耗FPGA
• 移动设备、嵌入式应用前景看好，带动接口IC需求
• 高速通信接口升级引发测试新需求Ojyesmc
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16 GT/s速率的第四代PCIe预计在2015年第一季完成，目前的进展为0.3版本；未来将主要应用于服务器，支持40/100G以太网络、 Infiniband等。在此同时，PCI SIG也发表了3.1版第三代PCIe的功能强化，包括已经应用于英特尔Haswell处理器的L1功耗模式、更佳的媒介同步与虚拟化改善。
16 GT/s速率的第四代PCIe
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PLDA 以采用Altera与Xilinx的FPGA迷你开发板展示第二代PCIe
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Teledyne LeCroy 展示低价位(5,000美元有找)的第二代PCIe协议分析仪
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本文授权编译自EE Times，版权所有，谢绝转载
编译：Judith Cheng
参考英文原文：Slideshow: PCIe takes on mobile, Thunderbolt, more，by Rick Merritt
相关阅读：
• Altera推出业界首款符合5Gbps PCIe Gen2要求的低功耗FPGA
• 移动设备、嵌入式应用前景看好，带动接口IC需求
• 高速通信接口升级引发测试新需求Ojyesmc
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Slideshow: PCIe takes on mobile, Thunderbolt, more
Rick Merritt
PCI Express Gen 3 will ride the MIPI M-PHY in tablets and smartphones thanks to one of several new specs from the PCI SIG. SANTA CLARA, Calif. – The spec is done for a mobile interconnect that will pack PCI Express into smartphones and tablets. Cadence and Synopsys showed working silicon for the M-PCIe interface at the annual meeting of the PCI Special Interest Group here.
The spec lets PCIe protocols ride the M-PHY defined by the MIPI trade group and already widely used in mobile devices. OEMs will adopt the interface to lower costs and shrink development times by reusing PCIe software to replace a wide variety of mobile interconnect protocols.
Separately, the PCI SIG expects to finish work before June 2014 on OcuLink, a 32 Gbit/second cabled version of PCIe. It aims to deliver more bandwidth than the rival Thunderbolt interconnect backed by Apple and Intel at “orders of magnitude lower cost,” said Ramin Neshanti, marketing workgroup chair of the PCI SIG.
In addition, the group announced progress on its Gen 4.0 spec, expected to be the last turn of the crank for copper in pcb interconnects. It will support 16 GTransfers/second and be complete in early 2016.
The SIG also detailed a handful of enhancements to the 8GT/s Gen 3 spec and a new form factor for mobile devices called M.2 that aims to replace mini-PCIe cards.
The M-PCIe news took center stage at the event. It is expected to appear in apps processors, Wi-Fi combo devices, bridge chips and storage controllers. First SoCs using it could tape out early next year, said a Cadence product manager.
Cadence showed M-PCIe running at Gear 2 data rates up to 2.9 GHz.
M-PCIe hits 5.8 GHz
Synopsys showed M-PCIe running at Gear 3 data rates up to 5.8 GHz. A Gear 4 data rate matching the 8 GT/s of PCIe Gen 3 is in the works at MIPI.
A spec written in shorthand
The M-PCIe spec is only 60 pages long, terse by comparison to other PCI SIG standards. That’s because it largely references existing MIPI M-PHY and PCI-SIG Gen 3 protocol specs. It aims to link apps processors with basebands, W-Fi combo chips, storage and more (below).
Click on image to enlarge.
A smaller Mini Card
Click on image to enlarge.
The M.2 spec defines as many as a dozen form factors that can replace existing Mini and Half Mini PCIe cards for Wi-Fi combo chips, solid-state drives and other peripherals. The version 0.7 spec could be complete by the end of the year.
PCIe attacks Thunderbolt
Click on image to enlarge.
Oculink is a cabled PCIe Gen 3 that will deliver up to 32 Gbits/s (using a x4 configuration) over 1-3 meters of a low-cost twisted pair cable with the spec due for complete before June 2014.
Oculink will support PCIe Gen 4 and active optical cables in the future. It aims to outgun and undercut Thunderbolt, launched in early 2011 at 20 Gbits/s.
Speed doubler in the pipeline
Click on image to enlarge.
The 16 GT/s PCIe 4.0 should be complete in Q1 2015, is in a version 0.3 today and should “not require heavy equalization,” said a Neshanti. It will see use mainly in servers for 40/100 Gbit Ethernet, Infiniband and more.
Meanwhile, the PCI SIG is rolling up a number of Gen 3 enhancements into a 3.1 version. They include an L1 power state already used in Intel’s Haswell processor, better media synchronization and refinements for virtualization.
Tiny board packs punch
PLDA showed at the event its tiny Altera and Xilinx FPGA boards supporting PCI3 Gen 2.
Low cost PCIe tester
Teledyne LeCroy shows a PCIe Gen 2 protocol analyzer that sells for less than $5,000.
责编：Quentin
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