未来十年晶体管成本降速趋缓，半导体价格或提高

摩尔定律(Moore's Law)将在未来的十年持续发展，但每单位晶体管成本下跌的速度将随之减缓，无法再像过去一样快速降低了。根据新思科技董事长兼首席执行官Aart de Geus表示，芯片设计越来越复杂，逐渐推迟向更大晶圆的过渡，但也为其他替代技术开启了大门。 Aart de Geus的这番评论正好出现在当今业界日益关注半导体技术的未来发展之际。有些业界观察家指出，28nm节点可能会是最后一次还能以新硅晶制程为客户带来完整的好处了──更低成本、功耗以及更高性能。 展望未来，“评判的标准将取决于每个晶体管成本降价的速度有多快──这同时也会是良率能多快提升的函数，”Aart de Geus指出，“随着晶体管降价速度减缓，半导体的价格很可能就必须提高，”才能使芯片制造商得以回收投资。 不过，Aart de Geus也转述英特尔资深院士Mark Bohr的看法，他说Mark Bohr表示看到一条可迈向7nm节点的发展道路，还“可能以某种方式降低每晶体管价格。” 业界分析师G. Dan Hutcheson则指出，目前对于未来节点的每晶体管成本资料掌握有限。不过，根据以往的发展经验，他预计业界将能持续看到成本下降。 Hutcheson指出，由于缺少下一代微影工具，晶圆厂自20nm起就必须为一些芯片层进行两次图样(pattern)过程。但微影技术仅占芯片制造成本的四分之一。 面对未来可能更高的成本，“业界将竭尽所能的利用目前的28nm节点，”Aart de Geus表示，“由于利润并没那么高，其他公司可能更指望在16/14nm节点，因此，只有一些厂商会转移到20nm节点，”他补充说。 这可能会为其他替代技术开启了另一扇门，如意法半导体(ST)以及其他业者提出的全耗尽型绝缘上覆硅(FD-SOI)技术。“但这也会带动其他主导厂商大力支持 FD-SOI ，”他说。 考虑到成本不断的增加以及芯片制造的复杂度，半导体公司已经将从300mm晶圆过渡到45nn晶圆的时程延迟到2020年了。Aart de Geus说：“更大的晶圆有时虽可带来更低成本，但业界也相应地需要一款完整的工具，如今却还无法到位。” 尽管如此，Aart de Geus对于未来发展仍抱持乐观看法。随着该公司推出重要的芯片设计软件升级，他表示，“我们可支持多几十亿种晶体管芯片，而在未来十年也将看到持续的进展。” 有趣的是，在以Synopsys公司工具完成的设计中，只有约5%的设计采用目前先进的28nm制程技术。根据Aart de Geus的简报数据，180nm节点是目前最普遍的制程技术，在采用该工具的设计中约占30%，接着分别是65nm以及250nm节点。 “这的确是令人惊讶的数据分布，让我不得不再三确认图表与数字是否确，”Aart de Geus说，“但可以确定的是我们看到了大量转向28nm的趋势，接下来也将逐渐增加过渡至16/14nm节点。”支持原创，鄙视抄袭，请访问《国际电子商情》网站www.esmchina.com 本文授权编译自EE Times，版权所有，谢绝转载 编译：Susan Hong 参考英文原文：Transistor-Cost Declines Slowing, Synopsys Says，by Rick Merritt

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{pagination} Transistor-Cost Declines Slowing, Synopsys Says Rick Merritt SANTA CLARA, Calif. — Moore's Law will continue for the next decade, but declines in cost/transistor won't be as great as they were in the past, said Synopsys chairman Aart de Geus. Growing complexity of chip designs is delaying a shift to larger wafers and may open doors for alternative technologies, he said at an annual event for Synopsys users. His comments come at a time of increasing concern about the future of semiconductor technology. Some observers say the 28nm node could be the last to deliver the full range of benefits traditional with a new silicon node -- lower costs and power and higher performance. Looking ahead, "the jury is out in how fast price comes down per transistor -- that's a function of how quickly yields improve," de Geus told a press gathering here. "It is possible that as the price decrease of transistors lowers, the price of semiconductors has to go up" so chip makers can recoup their investments, he said. de Geus said he contacted Mark Bohr to get the Intel fellow's views. Bohr said he sees a path to a 7nm node and the "possibility of somehow lowering the price per transistor," de Geus reported. Analyst G. Dan Hutcheson said little data is available about the cost/transistor in future nodes. However, he is projecting the industry will continue to see cost declines based on its past history. Starting at 20nm, fabs have to pattern some chip layers twice due to the lack of next-generation lithography tools. But lithography only represents roughly a quarter of the cost of making a chip, Hutcheson said. Bunching up at 28nm In the face of potentially higher costs, "people will try to use today's 28nm node as much as they can," de Geus said. "Only a few people will move to the 20nm node [because its] benefits are not that high, so they will wait for 16/14nm nodes," he added. That could open the door to alternatives such as the fully depleted silicon-on-insulator technology proposed by STMicroelectronics and others. "But it would take [other] major players to put their weight behind" FD-SOI for it to take off, he said. Given the increasing costs and complexity of making chips, semiconductor companies have put off a shift from 300 to 450 mm wafers until 2020, he said. Larger wafers can sometimes provide lower costs but they also require "a complete retooling of the industry and that's not happening right now," he said. Nevertheless, the Synopsys executive remained upbeat at the event where he launched an upgrade of the company's main chip design software. "We support multiple billion-transistor chips, and we will see a continuation of that work for the next ten years," he said. Interestingly, only about five percent of the designs done in Synopsys' tools are at today's leading-edge 28nm process, according to one foil in de Geus's keynote. The 180nm node is the most popular, used by nearly 30% of the designs using its tools, followed by the 65nm and 250nm nodes. "It's an amazing spread -- I had to look twice at that graph to make sure the numbers were correct," de Geus said. "We do see the bulk of the designs gradually moving up and I think that will continue, but we will see a bunching up at 28nm and then slowly an increase to the 16/14nm nodes," he said.