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未来内存技术谁最主流?IBM说是PCM

IBM最近展示了如何将相变化内存(PCM)整合到固态内存阶层架构(hierarchy),并展示了第一款采用 PCIe 接口的相变化内存储存系统主板原型;在下一代主流内存技术争霸战中,相变化内存似乎已经占据优势。

IBM最近展示了如何将相变化内存(PCM)整合到固态内存阶层架构(hierarchy),并展示了第一款采用 PCIe 接口的相变化内存储存系统主板原型;在下一代主流内存技术争霸战中,相变化内存似乎已经占据优势。 在一场于2014年非挥发性内存研讨会(2014 Non-Volatile Memory Workshop)的简报中,IBM介绍了相变化内存储存系统架构,并以闪存固态硬盘(SSD)做为比较;在各方面的比较上,相变化内存都略胜闪存一筹。此外该公司提出了一款服务器系统设计,以结合闪存数组与相变化内存数组的内存阶层架构来取代硬盘(HDD)。 “我们是以闪存固态硬盘与相变化内存PCIe储存卡,在两种设备的系统层级进行比较;”IBM储存系统研究小组成员Ioannis Koltsidas表示,该公司所合作的希腊帕特雷大学(University of Patras),以古希腊神话中的英雄特修斯(Theseus)来为相变化内存储存卡命名。 而研究人员是拿相变化内存PCIe储存卡与两款闪存固态硬盘──包括一款企业级产品与一款消费性产品──进行比较,发现两款固态硬盘的访问时间,分别是相变化内存储存卡的12倍与275倍。

《国际电子商情》IBM储存系统研究小组成员Ioannis Koltsidas展示相变化储存系统电路板原型
IBM储存系统研究小组成员Ioannis Koltsidas展示相变化储存系统电路板原型
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虽然相变化内存芯片在 2012年左右就已经问世,但实际布署的案例非常少,也听到业界出现少数对其可靠性的抱怨;无论如何,IBM显然十分看好相变化内存前景,但人们可能也会认为,相变化内存需要先解决一些技术上的问题。 相变化内存的最大优势在于访问速度高于闪存,但仍稍逊于DRAM;此外相变化内存也拥有非挥发性。而相变化内存的正常输入/输出(I/O)吞吐量,在硬盘的每秒I/O运作效率降低时可维持上升,有机会取代目前闪存所扮演的角色。 快 闪内存正面临扩充性(scalability)的问题,重复写入次数最多约为1万次;相变化内存的可扩充性则不断提升,重复读写次数可高达1,000 万次──而若是透过前向纠错(forward error correction)技术,甚至可将重复读写次数提升到10兆(trillion)次。

《国际电子商情》IBM表示,相变化内存(蓝色部分)能整合至大多数服务器与储存系统的内存阶层中
IBM表示,相变化内存(蓝色部分)能整合至大多数服务器与储存系统的内存阶层中
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相 变化内存是采用在两个电极之间夹着硫化物合金(chalcogenidic alloy)的三明治结构,高电流会将硫化物合金转为非晶(amorphous)型态(代表0),而中电流则会将之转换为结晶型态(代表1),低电流则允许其状态被读取。其0与1的程序化时间分别为70纳秒(nanosecond)与120纳秒;IBM所测试的储存系统之相变化内存采用90纳米制程,时脉频率66MHz。 本文授权编译自EE Times,版权所有,谢绝转载 编译:Judith Cheng 参考英文原文:IBM Hawks PCM for Storage,by R. Colin Johnson

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{pagination} IBM Hawks PCM for Storage R. Colin Johnson PORTLAND, Ore. -- IBM recently demonstrated how to integrate phase change memory (PCM) into a solid-state memory hierarchy, and it has shown its first PCIe-based prototype board for storage systems. It's looking like speed and the ancient Greek heroes are on PCM's side. In a presentation at the 2014 Non-Volatile Memory Workshop, IBM described its architecture, compared it to flash-based solid-state drives (SSDs), and proposed a server system that eliminated the hard-disk drive (HDD) in favor of a memory hierarchy using both flash-based arrays and PCM-based arrays. In comparisons, the PCM-based arrays handily beat flash. Ioannis Koltsidas, an IBM storage systems research staff member, shows his prototype board that outperforms flash alone by adding phase change memory (PCM). (Source: IBM) "The comparison was between flash SSD and our PCM PCIe card -- it was a comparison at the system level of the two storage devices," Ioannis Koltsidas, a member of the IBM storage systems research staff, told EE Times. Working with the University of Patras in Greece, which helped name the card Theseus after a hero in Greek mythology, the researchers compared the PCM-based PCIe card with two flash SSDs -- an enterprise-grade flash SSD and a consumer-grade flash SSD. "We found the times for the two flash SSDs to be 12x and 275x longer than for the PCM PCI-e card." Though PCM memory chips have been around since 2012, there have been very few deployments and quite a few complaints about reliability. Nevertheless, IBM appears to be gung ho about the possibilities of PCM-based memories, one would assume, after the bugs are worked out. PCM (blue) can fit into many slots in the memory hierarchy for servers and storage systems, according to IBM. The biggest advantage of PCM over flash is that its performance is higher than flash, though not as high as DRAM, plus it enjoys the nonvolatility of flash. Also, PCM normalized input/output (I/O) throughput is on the rise at a time when HDD I/O operations per second are waning. Today flash is filling the gap, but PCM could take over that job. Flash is also facing scalability problems and can only be rewritten about 10,000 times at the most. PCM's scalability is on the rise, and it can be rewritten at least 10 million times -- or, with forward error correction, at least 10 trillion times. PCM uses a chalcogenidic alloy sandwiched between two electrodes. A high current turns the chalcogenidic alloy amorphous (representing a 0), whereas a medium current turns it crystalline (representing a 1), and a low current allows its state to be read out. Programming times for 0s and 1s are 70 nanoseconds and 120 nanoseconds, respectively. IBM's tests used PCM memories fabricated at a relaxed feature size of 90 nanometers and a clock frequency of 66 megaHertz.
责编:Quentin
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