IBM开发出可模拟人脑的芯片

至今全世界最像人脑的计算机芯片一直由IBM所主导开发，该公司在Cornell Tech与iniLabs, Ltd等公司的携手合作下，为美国国防部先进研究计划署(DARPA)的神经形态自适应塑料可微缩电子(SyNAPSE)系统计划打造先进的“类人脑芯片”。 这种半导体将来可能应用于研发即使没有人类命令也能自己学习，进而解决问题的人工智能。“当我们在六年前启动 SyNAPSE 计划时，很多人认为不可能实现，”IBM院士兼IBM Research脑启发运算研究中心首席科学家Dharmendra Modha表示，“但是现在我们已经证明它是可能的，而且我们正致力于使其于未来实现商业化。”相关内容发表在8月8日的美国《科学》杂志上。 人类大脑的神经细胞由无数被称为“突触(synapse)”的组织连接起来，能传递信息和进行记忆。大脑尽管体积有限，但能够以微量的能量完成复杂的工作。有分析认为如果制成模拟大脑的半导体芯片，就能开发出能完成人类大脑同样工作的计算机。 IBM的SyNAPSE芯片拥有1百万个人工神经元(类脑细胞)和2.56亿个突触(储存单元)，以及4,096个称为“神经突触”(neurosynaptic)的处理核心执行作业，并整合内存、运算、通讯，以及以一种异步事件驱动、平行与容错的方式作业。根据这种技术制造出的半导体从设计理念上就不同于现有计算机使用的半导体芯片。

IBM的neurosynaptic处理器在单一芯片上整合了1百万个神经元以及2.56亿个突触。
Source：IBMFAvesmc

本文授权编译自EE Times，版权所有，谢绝转载 本文下一页：比当今微处理器所需功率低5000倍以上 {pagination} “这款处理器整合了54亿个晶体管，可说是IBM有史以来最大的芯片，而且，据我们所知是至今全世界最大型的芯片，但功耗仅70mW，”Modha说。研究团队利用试制的半导体芯片，成功完成了对人物图像等的识别工作。 为了衡量这一庞大的芯片的性能，IBM发明了一种新的度量标准——每秒突触运算(synaptic operations per second；SOPS)，以取代每秒浮点运算(FLOPS)性能。 “该芯片可提供每瓦460亿的SOPS，这款相当于一张邮票大小的超级计算机重量却轻如羽毛，所需的电源也仅约一款助听器的用量，”Modha说，“它可作为监控传感器、移动设备、执行云端服务以及超级运算的理想应用。” 该架构每平方公分消耗20mW功耗，比当今微处理器所需的功率更低5,000倍以上。该芯片架构基于先前在每个neurosynaptic核心中内含256 个神经元的上一代芯片。而在这款第二代芯片中，IBM不仅为其缩减了15倍的芯片面积、功耗降低100倍，同时还为每个芯片增加至4096个核心。 该 核心由芯片上网状网络以及相邻芯片间直接链接的方式进行连结。各芯片之间无缝地彼此连接，以期形成未来neurosynaptic超级计算机的基础。此外， 为了证明其可扩展性，IBM并展示了一款16芯片的系统，可将芯片架构扩展至1,600万个可编程的神经元以及40亿个可编程的突触，其终极目标在于达到 人脑神经系统所需的100兆或更多个突触。 “我们认为，这款芯片为这款具有全新架构、无与伦比的规模、速度、功效和可扩展性的neurosynaptic计算机，建立了一个全新的里程碑，”Modha说。

该芯片(左)布局是由64x64个神经突触核心数组组成，每个核心(右)内含256颗神经元以及65,536个突触，以实现密集运算、储存与通讯。
Source：IBMFAvesmc

本文授权编译自EE Times，版权所有，谢绝转载 本文下一页：“非诺伊曼型”的新一代半导体 {pagination} 被誉为“计算机之父”的数学家冯·诺伊曼（von Neumann）于1946年提出计算机构想。之后的计算机都采取根据事先存储的程序，逐步执行命令的模式。这种计算机被称为“诺伊曼型”。从设想提出直到如今，所有的计算机都采用了诺伊曼型。不过，对半导体进行微细加工，以提升计算机处理速度这一传统方式在加工技术方面正在趋近极限。 IBM 表示，经由整合处理、储存与通讯，目前已能消除令人生畏的“冯·诺伊曼”瓶颈––迫使传统微处理器求助于多层次功耗快取。而且，由于所有的核心以平行方式执行，不必再以GHz级的功耗作业。事实上，1kHz芯片 频率可用于离散神经元动态。而藉由在整个芯片上平均分散核心，使该架构具备容错能力；任何核心错误都不至于影响运算结果。 IBM为了突破极限，除了模拟大脑之外，还应用了量子力学的原理，一直在致力于研究被称为“非诺伊曼型”的新一代半导体。IBM认为这次的成果是对约10年研究的重大总结，认为将来有望开发出以扭扣电池驱动的邮票大小的超级计算机。

为了展示芯片至芯片的无缝通讯能力，IBM构建出一款16芯片以单一网络测试的电路板。
Source：IBMFAvesmc

本文授权编译自EE Times，版权所有，谢绝转载 本文下一页：研究芯片可适应现实世界的学习能力 {pagination} 该芯片采用三星(Samsung)的28nm制程制造，以实现高密度的芯片内存与低泄漏晶体管性能。Modha表示该芯片第一次上电就能完美的运作。 Modha 的公司目前正忙于开发一款新的仿真器、新的编程语言、新的编程环境、新的工具库、新的算法以及新的教学课程，旨在创造一个全球化的应用生态系统。透过将操作数件移动至更接近传感器以及整合不同类型的传感器，研究人员们希望能够打造出具有更佳配备的neurosynaptic计算机，以便有效处理实时数据串流的多种意义。 “我们开始与大学以及业界合作伙伴共同讨论各种相关应用，例如在相机上内部对象辨识功能，或利用多传感器融合来实现听觉处理，”Modha说，”而在汽车和医疗设备中，可以采用收集的方式来处理数据，或者是能完全意识环境变化的智能手机等应用。”

该芯片的低功耗与感测处理性能使其相当适于医疗、机器人、感测以及个人导航等多元化的应用。
Source：IBMFAvesmc

IBM并致力于研究芯片可适应现实世界变化的学习能力。该公司计划利用在内存密度方面的CMOS进展、3D整合以及新的传感器技术，以实现更低功耗、更紧密的封装以及更快的速度。 这项研究计划经费约5,300万美元，分为四个阶段进行，并由DARPA提供赞助。该计划还将探索可在未来五年内实现商用化的可能性。 本文授权编译自EE Times，版权所有，谢绝转载 编译：Susan Hong 参考英文原文：IBM Puts Brain On-a-Chip，by R. Colin Johnson {pagination} IBM Puts Brain On-a-Chip R. Colin Johnson PORTLAND, Ore. -- The most brain-like computer chip to date has been produced by IBM for the Defense Advanced Research Project Agency's (DARPA's) Systems of Neuromorphic Adaptive Plastic Scalable Electronics (SyNAPSE) program, in collaboration with Cornell Tech and iniLabs, Ltd. "When the SyNAPSE project was launched six years ago, many people thought it was impossible," Dharmendra Modha, an IBM fellow and chief scientist of brain-inspired Computing at IBM Research, told EE Times. "But today we have proven that it is possible, and we are working toward making it a commercial reality in the future." The IBM SyNAPSE chip has 1 million artificial neurons (brain-like cells) and 256 million synapses (storage cells), all powered by 4,096 neurosynaptic cores integrating memory, computation, communication, and operating in an asynchronous event-driven, parallel, and fault-tolerant manner. IBM's neurosynaptic processor integrates 1 million neurons and 256 million synapses on a single silicon chip. (Source: IBM) "With 5.4 billion transistors, it is the biggest chip IBM has ever made, and as far as we know is the biggest chip anyone has ever made, and yet it consumes just 70 milliWatts of power," Modha said. To measure the performance of this mammoth chip, IBM had to invent a new metric, synaptic operations per second, (SOPS) to replace floating point operations per second (FLOPS). "The chip delivers 46 billion SOPS per Watt -- literally a supercomputer the size of a postage stamp, with the weight of a feather and using a power source the size of a hearing aide battery," Modha said. "It's ideal for monitoring sensors, mobile devices, executing cloud services, and supercomputing." The architecture consumes 20 milliWatts per square centimeter, which is more than 5,000 times cooler than the power required by today's microprocessors. This chip's architecture is based on an earlier chip with a single neurosynaptic core containing 256 neurons. In this second-generation chip, IBM reduced the area by 15 times, reduced the power by 100 times, and increased the number of cores per chip to 4,096. The cores are connected by an on-chip mesh network with direct connections between adjacent chips. When tiled, they seamlessly connect to one another in order to form a foundation for future neurosynaptic supercomputers. To demonstrate its scalability, IBM showed a 16-chip system which extended the architecture to 16 million programmable neurons and 4 billion programmable synapses, with the eventual goal of achieving human brain-sized systems of 100 trillion synapses or more. "We believe this chip establishes a new landmark in neurosynaptic computers with a radical new architecture, unparalleled scale, speed, power efficiency, and boundless scalability," Modha said. The layout of the chip (left) is composed of 64x64 array of neuro-synaptic cores, each of which (right) implements 256 neurons and 65,536 synapses for tightly integrated computation, memory, and communication. (Source: IBM) By integrating processing, memory, and communications on each core, IBM claims to have eliminated the dreaded von Neumann bottleneck that forces traditional microprocessors to resort to multiple levels of power-consuming caches. And since the cores all operate in parallel, they don't have to operate at power-consuming gigaHertz rates. In fact, the only clock on the chip is a 1kHz clock to discretize neuron dynamics. And by distributing the cores across the chip, the architecture is fault tolerant; any core can fail without affecting the outcomes of computations. To demonstrate the ability to connect chip-to-chip communication seamlessly through tiling, IBM build a board where 16 chips were tested as a single network. (Source: IBM) The chip was fabricated using Samsung's 28-nanometer process known for its dense on-chip memory and low-leakage transistors. Modha said it worked flawlessly the first time it was powered up. His company is busy creating a new simulator, a new programming language, a new programming environment, new libraries, new algorithms, and a new teaching curriculum aimed at creating a global ecosystem of applications. By moving the computing elements closer to the sensors and integrating different types of sensors, the hope is that neurosynaptic computers will be better equipped to deal with the ambiguity of real-time data streams. "We are beginning to talk to university and industrial partners about all sorts of applications, such as object recognition built into cameras, or auditory processing using multi-sensor fusion," Modha said. "And in automobiles or medical devices, the data could be processed as it is being collected, or smartphones that are totally aware of their environment." The low-power and sensory processing capabilities of this chip make it well suited for diverse applications (from left to right) in medicine (a smart thermometer that visually inspects the throat and sniffs for telltale odors of infection), robotics (an autonomous rolling robot studded with video cameras can inspect a disaster site), sensing (floating jellyfish-like sensors that measure water temperature, salinity, turbidity, and wave height) and personal navigation (assistive glasses that can help the visually impaired navigate complex environments). (Source: IBM) IBM is also working to demonstrate on-chip learning capabilities that adapt to the real world. It plans to take advantage of CMOS advances in memory density, 3-D integration, and new sensor technologies to enable even lower power use, denser packaging, and faster speeds. The funding totaled $53 million over four phases from DARPA. The program is exploring commercial possibilities that could be realized within the next five years.