在英特尔(Intel)负责制程技术部门的高层Mark Bohr指出，无晶圆厂(fabless)半导体业经营模式已经快到穷途末路。他认为，台积电(TSMC)最近宣布只会提供一种20nm制程，就是一种承认失败的表示；而且该晶圆代工大厂显然无法在下一个主流制程节点提供如 3D晶体管所需的减少泄漏电流技术。
“高通(Qualcomm)不能使用那种(22nm)制程技术；”Bohr在日前于美国举行的 Ivy Bridge 处理器发表会上宣布，该新款处理器是采用英特尔三闸22nm制程生产。他在会后即兴谈话中对笔者表示：“晶圆代工模式正在崩坏。”
当然，英特尔会想让这个世界相信，只有他们能创造世界所需的复杂半导体技术，而为其竞争对手高通、AMD代工的台积电与GlobalFoundries都不能。在Ivy Bridge处理器发表会上，英特尔所述说的公司成功故事，其秘诀之一就是来自于制程技术与芯片设计者之间的紧密关系。
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英特尔客户端PC事业群新任总经理Kirk Skaugen在发表会上与Bohr、还有Ivy Bridge项目经理Brad Heaney一同主持问答时间；这款处理器除了首度采用3D晶体管架构，也是英特尔第一次以High-K金属闸极制程制造的产品。“作为一家整合组件制造厂(IDM)，确实有助于我们解决生产这样一款小尺寸、复杂组件时所遭遇的问题。”Bohr表示。
在当下我没有质疑他的说法。自从进入次微米制程时代，EETimes美国版就有不少文章谈到芯片设计业者与制程技术提供者之间，需要有更紧密的合作关系；一位来自Nvidia的实体设计部门高层也在最近Mentor Graphics的年度会议上，强调了相同的论点。
不过，Bohr在指称晶圆代工厂与无晶圆厂芯片设计业者无法追随英特尔的脚步时，似乎是过度延伸了该论点。笔者听过台积电与GlobalFoundries 的研发主管提出很好的例子，证明3D晶体管架构在14nm制程节点之前并非必要；台积电并曾表示，20nm节点并没有足够的回旋空间，可创造高性能制程与低耗电制程之间的明显变化。
本文下一页：高通缺货说明了一些问题
本文授权编译自EE Times，版权所有，谢绝转载
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• 28nm产能告急，高通大订单花落谁家
• 两岸半导体厂商合作，才能御外敌
• 2012晶圆代工收入可增长12%，但面临三大挑战E2fesmc
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我忘了问Bohr英特尔是否已在22nm节点将高性能制程(high performance)与低耗电(low power)制程做区别，不过他在问答时表示，英特尔已经完成了一个特别针对SoC组件生产的制程技术版本，该公司计划在每个主流制程技术完成后，进一步于一季或是两季之后推出该SoC版本的变形。
对于台积电的20nm制程计划，高通不会发表评论；但高通确实在最近财务季报发表会上表示，该公司无法向台积电取得足够的28nm制程产能以因应市场需求，因此正寻求多个新代工来源，并预期能在今年稍晚正式上线。
这对GlobalFoundries、联电(UMC)等其它代工厂来说是个好机会；不过Bohr认为，由于生产28nmSoC需要在设计细节上有更紧密的交流，对高通来说，与同样有生产手机SoC (Exynos)的竞争对手三星(Samsung)的代工伙伴合作，其风险会大过于任何机会。
笔者询问Bohr，英特尔除了提供22nm制程给两家已公开的伙伴Achronix 与 Netronome之外，是否还有其它的合作对象；但他只回答，英特尔并不想涉足晶圆代工业务，只是让少数几家策略伙伴取得其技术。
英特尔可能没办法独占聪明的制程工程师或设计工程师，但显然拥有一些杰出的员工，已学会如何巧妙地自我行销；Bohr与Heaney就现身于发表会上放映的搞笑影片中，他们两个被微缩，进入一颗Ivy Bridge芯片中游历。
展望未来，Bohr表示英特尔已经使用浸润式微影技术，完成下一代14nm节点制程的特性描述；其成果不只是“令人振奋”而已，也意味着该公司可望将浸润式微影技术运用到仍在初期计划阶段的10nm节点：“我们认为已经找到在10nm节点运用浸润式微影技术的解决方案──我们也很乐意使用超紫外光(EUV)微影技术，但不抱太大期望。”
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接着笔者又问道，英特尔是否会在14与10nm节点拥有一些像是3D晶体管这样的新花招，他简单回答：“是。”…当一家公司赞扬其高阶工程师并提供与他们接触的机会时，真的是很不错，但我实在是很不爱看到这些人被一家公司的公关部门“训练有素”的模样。
编译：Judith Cheng
本文授权编译自EE Times，版权所有，谢绝转载
参考英文原文：Intel exec says fabless model “collapsing”，by Rick Merritt
相关阅读：
• 28nm产能告急，高通大订单花落谁家
• 两岸半导体厂商合作，才能御外敌
• 2012晶圆代工收入可增长12%，但面临三大挑战E2fesmc
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Intel exec says fabless model 'collapsing'
Rick Merritt
SAN FRANCISCO – It’s the beginning of the end for the fabless model according to Mark Bohr, the man I think of as Mr. Process Technology at Intel.
Bohr claims TSMC’s recent announcement it will serve just one flavor of 20 nm process technology is an admission of failure. The Taiwan fab giant apparently cannot make at its next major node the kind of 3-D transistors needed mitigate leakage current, Bohr said.
“Qualcomm won’t be able to use that [20 nm] process,” Bohr told me in an impromptu discussion at yesterday’s press event where Intel announced its Ivy Bridge CPUs made in its tri-gate 22 nm process. “The foundry model is collapsing,” he told me.
Of course Intel would like the world to believe that only it can create the complex semiconductor technology the world needs. Not TSMC that serves competitors like Qualcomm or GlobalFoundries that makes chips for Intel’s archrival AMD.
Intel used the Ivy Bridge event to spin the tale of how part of the secret to its success is its close partnership between process and chip designers.
Kirk Skaugen, the new general manager of Intel’s client PC group, moderated a Q&A with Bohr and Brad Heaney, the Ivy Bridge program manager. In addition to working together on Intel’s first CPUs using 3-D transistors, the two collaborated on Intel’s first processors using high-K metal gate technology.
“Being an integrated device manufacturer really helps us solve the problems dealing with devices this small and complex,” Bohr said in the Q&A.
I don’t doubt that for a minute. Since the dawn of submicron design, EE Times has been writing about the need for ever closer collaboration between chip and process designers. An Nvidia physical design exec underlined the same point in a recent talk at Mentor Graphics’ annual user group meeting.
But Bohr stretches the point too far when he says the foundries and fabless companies won’t be able to follow where Intel is going. I have heard top TSMC and GlobalFoundries R&D managers make a good case that 3-D transistors won’t be needed until the 14 nm generation. For its part, TSMC said at 20 nm there is not enough wiggle room to create significant variations for high performance versus low power processes.
I neglected to ask Bohr whether Intel has separate high performance and low power processes in its 22 nm technology. (Anyone from Intel is welcome to chime in here.)
However, in an open Q&A, Bohr said Intel has completed work on an SoC-specific version of its process technology. It plans going forward to have an SoC variant a quarter or two after each main process is complete.
For its part, Qualcomm would not provide its opinions on TSMC’s 20 nm plans. The company did say in its recent quarterly earnings call it can’t get enough 28 nm technology from TSMC to meet product demand, so it is working to develop multiple new sources it expects will come online later this year.
That’s a big opportunity for a GlobalFoundries, UMC or other fabs to step up. Given the close sharing of design details required to make 28 nm SoCs, it’s more of a risk than an opportunity for Qualcomm to work with Samsung’s foundry folks, Bohr said, given Samsung has its own Exynos mobile SoCs.
I asked Bohr to whom Intel is providing access to its 22 nm process besides two announced partners—Achronix and Netronome. He only said that Intel does not want to be in the general foundry business, but it makes its technology available to a few strategic partners.
Intel has no monopoly on smart process technology engineers and designers. But it does have some brilliant ones, and it has learned to market them smartly. Bohr and Heaney even appeared yesterday in another one of Intel’s playful videos shrinking the two engineers so they could tour the insides of an Ivy Bridge chip.
Looking ahead, Bohr said Intel has finished characterizing its next-generation 14 nm process using immersion lithography. It even has “encouraging results” suggesting it will be able to use immersion litho for the 10 nm node that is still in early planning phase.
“We think we have a [10nm] solution using immersion lithography—we’d love to have extreme ultraviolet [EUV] lithography, but we are not counting on it,” said Bohr in the event Q&A.
As a follow up, I asked whether Intel has other new process tricks like 3-D transistors at 14 and 10 nm. His answer: “Yes!”
I love it when companies celebrate and provide access to their top engineers. But I hate it when they are so well trained by their PR departments.
