制程技术向7nm大跃进，3D IC硬着头皮也要上

GlobalFoundries 公司正在仔细考虑其 20nm 节点的低功耗和高性能等不同制程技术，而与此同时，多家芯片业高层也齐聚一堂，共同探讨即将在2014年来临的 3D IC ，以及进一步往 7nm 节点发展的途径。 IBM 的专家指出，下一代的20nm节点可支持最佳化的低功耗和高性能制程技术。而 GlobalFoundries 将在今年八月决定，是否提供这些不同的制程选项。 这些仅仅是今年度 GSA Silicon Summit 上讨论的两个焦点。与会的芯片业高层还讨论了预计在2014年到来，但仍面临诸多挑战的 3D IC ，以及脚步缓慢但仍然预见可朝 7nm 迈进的 CMOS 微缩技术。 “台积电最近表示其 20nm 节点在制程最佳化方面并没有显著差异，但我并不这么认为，” IBM 院士暨微电子部门首席技术专家Subramanian Iyer说。“我相信，在相同的节点上，你可以拥有两种不同的制程，”他在主题演讲中表示。 事实上， GlobalFoundries 正在考虑是否是在为 20nm 提供高性能和低功耗制程。 “我们仍在与主要客户讨论该做些什么，针对性能和功耗方面，可能要做出更多取舍，” GlobalFoundries 先进技术架构主管Subramani Kengeri表示。 他指出， 20nm 的变化空间可能相对更加狭小，而且从经济面来看也未必可行。IBM的Iyer则认为，台积电决定仅提供一种20nm制程，其经济面的考量可能多于技术面。 接下来，采用FinFET的14nm制程，则将为芯片产业开创更大的机会，如提供0.9V的高性能版本，以及0.6V的低功耗变种制程等。此外，与传统转移到一个新制程节点相较，14nm节点可提供的利益也预估将高出两倍之多。 从历史角度来看，要为每一个节点提供不同制程变化，都会需要在基础制程上添加独特且复杂的特性，IBM的Iyer说。他指出，过去，我们在每一代制程节点都拥有不同功能的制程，现在不大可能骤然让它们完全消失。

20nm仍有变化空间，Subramanian Iyer说。I7yesmc

本文下一页：2014年，迎接3D IC到来 本文授权编译自EE Times，版权所有，谢绝转载

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{pagination} 2014年，迎接3D IC到来 此外，芯片业高层也探讨了几种可望在2014年量产，采用硅穿孔(TSV)的3D IC。 思科系统(Cisco Systems)封装专家暨技术品质部副总裁Mark Brillhart表示，3D IC将改变游戏规则。他认为3D IC将有几种不同的形式，而且很快就会步入大量应用。 “自1996年的覆晶封装技术热潮以来，我从未想象过封装技术能再次令人感到振奋，”Brillhart说。 高通(Qualcomm)“非常高兴”能在实验室中采用Xilinx的2.5D FPGA来开发原型，高通工程部副总裁Nick Yu表示。他预计，运用TSV来链接Wide I/O的高阶智能手机用行动应用处理器最快今年或明年便可问世。 “我们会在许多不同领域看到这些强大的3D技术，”IBM的Iyer表示，他们已经制造出了数款使用TSV堆栈处理器和DRAM的原型产品。 目前的CPU有8～12个核心，未来还将朝采用3D IC技术，堆栈24个核心与DRAM还有散热片的方向发展。IBM也对于‘在硅中介层上建构系统’(system on an interposer)的2.5D模块深感兴趣，在这些模块中，内存芯片在硅基板上围绕着处理器而建置，并使用去耦电容来改善功率调节性能。 “这个领域不断出现更多的创新，它们将带来更显著的差异化，但共同点在于它们都将提供适合行动应用的优势，”他补充说。 但3D芯片仍有许多待解的难题。工程师仍不知如何解决3D IC产生的热问题，他们需要新的测试策略和制造工具，他们也正在推动各领域的设计师们形成新的供应链，就各种技术和商业问题展开深入合作及探索。 “现阶段，成本是3D芯片面临的最大问题，”高通的Yu表示。 他表示，台积电提出的端对端(end-to-end) 3D服务会是低成本的说法并不能让他信服。他进一指出，不同的3D产品会需要不同的供应链。 “设备占单位成本很大一部份，”日月光集团(ASE Group)工程暨业务部资深副总裁Rich Rice说。该公司正在安装接合╱分离(bonding/de-bonding)、晶圆薄化和其它负责处理所谓3D制程中间步骤的设备。“即使是在较传统 的后段制程领域，当我们决定量产，我们也必须担负必要的资本支出，”Rice说。 应用材料(Applied Materials)发言人指出，业界需要新的3D系统，设备制造商正在努力准备为450mm晶圆和20、14nm节点做准备。 思科的Brillhart表示，他担忧的事情还有很多，包括为了找到让3D芯片获利的可行方法，彼此竞争的公司有时也必须合作。 本文下一页：摩尔定律步伐缓慢 本文授权编译自EE Times，版权所有，谢绝转载

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{pagination} 摩尔定律步伐缓慢 好消息是，专家们认为，一直到至少7nm节点，都不会出现根本性的障碍。但坏消息则是“更微小节点的优势正不断被侵蚀，”IBM的Iyer说。 罪魁祸首就微影技术。今天业界采用的193nm浸入式微影技术已经被要求用在22甚至14nm节点。 “这导致了愈来愈高的成本，”Iyer说。“另外，复杂的图形解决方案也让我们感到焦虑。” 微影成本确实会在20nm和14nm节点剧烈飙升，GlobalFoundries的Kengeri表示。他指出，额外的复杂性以及制程和设计成本，是让传统芯片产业每两年跨越一个技术世代的时程开始延长的主要原因之一。 业界多花费了三季的时间来达到符合品质要求的32/28nm技术节点，这要比过去所花费的时间多出一季，Kengeri说。“可看到整个产业的脚步正在趋缓，”他表示。 根据美林(Merrill Lynch)的报告，一个14nm的SoC项目成本可能会上扬到2.5亿美元，Marvell Semiconductor制造部副总裁Roawen Chen说。光罩成本约700万美元，且从投片到产出首个硅芯片的时间可能会延长到六个月，他表示。 “事实是它将变得更加昂贵，”Chen说。 但也有好消息，IBM的研究人员已经发现了制造出仅内含25个原子组件的方法，这为迈向7nm制程节点开启了全新道路。“在朝7nm前进的道路上，我们并没有看到根本性的问题存在，”Iyer说。 编译： Joy Teng 本文授权编译自EE Times，版权所有，谢绝转载 参考英文原文： Chip execs see 20 nm variants, 3-D ICs ahead ，by Rick Merritt

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• Achronix不走寻常路，首发22nm FPGA直面目标应用I7yesmc

{pagination} Chip execs see 20 nm variants, 3-D ICs ahead Rick Merritt MOUNTAIN VIEW, Calif. – Next-generation 20 nm processes can support optimized versions for low power and high performance, according to an IBM expert. GlobalFoundries will decide in August whether or not it will offer such variations. Those were just two data points from wide ranging discussions at the GSA Silicon Summit here. Separately, executives said a variety of 3-D ICs will hit the market in 2014 despite numerous challenges, and CMOS scaling is slowing down but still viable through a 7 nm node. “Recently TSMC said at 20 nm there are no significant differences [in process optimizations], but I don’t believe that,” said Subramanian Iyer, an IBM fellow and chief technologist in its microelectronics division. “I believe at same node you can have two [different variations],” he said in a keynote here. Indeed, GlobalFoundries is debating whether it wants to offer high performance and low power variants of a 20 nm process it is putting in place today. “We are still talking with lead customers to see what is the right thing to do, and there’s a lot of interest in performance and power trade-offs,” said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries in a brief interview with EE Times. The variations available at 20 nm may be relatively narrow and may not be economically viable, he said. Iyer of IBM said TSMC’s decision to offer one flavor of 20 nm may have been more of an economic than a technical decision. The follow-on 14 nm process using FinFETs will open up greater opportunities for a high performance version at up to 0.9 volts and a low power variant at down to 0.6 volts, Kengeri said. In addition, the 14 nm node could offer as much as twice the typical benefits of moving to a new node. The historic challenge of offering variations of a process is that each one requires a different set of unique and complex features added to the base process, said Iyer of IBM. “All the little features we have are like drugs, we can’t drop them without severe withdrawal symptoms,” he said. 3-D ICs coming in 2014 Separately, executives said several types of 3-D ICs using through-silicon vias (TSVs) will be in production in 2014. “This is a game changer,” said Mark Brillhart, a packaging expert and vice president of technology and quality at Cisco Systems, moderating a panel here. “I think 3-D ICs will be a differentiator and they will proliferate into a lot of applications,” he said. “I never thought packaging would be exciting again, but it’s like 1996 with flip chip all over again,” Brillhart said. Qualcomm is “very happy with” dense 2.5-D Xilinx FPGAs “we are playing with in the lab” for product prototyping, said Nick Yu, vice president of engineering at Qualcomm. He predicted mobile applications processors for high-end smartphones will hit the market this year or next using TSVs to link to Wide I/O memories. “This 3-D technology is really powerful and we will see it in many places,” said Iyer of IBM which has already made working prototypes of server processors in TSV stacks with DRAMs. CPUs have 8-12 cores now “and want to go to 24 cores” with 3-D IC modules that stack DRAMs and heat sinks. IBM is also interested in “systems on an interposer,” 2.5-D modules that surround a processor with memory chips on a silicon substrate with de-coupling capacitors to improve power regulation, he said. “There’s a lot of good stuff happening in this area that will make a significant difference, and the same concepts are applicable in the mobile space with similar advantages,” he added. The 3-D ICs also pose plenty of unsolved problems. They generate heat that engineers still don’t know how to dissipate, they require new test strategies and manufacturing tools and they require designers form new kinds of supply chains that collaborate on deeply detailed technical and business levels. “Cost is biggest issue of 3-D ICs right now,” said Yu of Qualcomm. He said he is not convinced TSMC’s proposed end-to-end 3-D service will be the lowest cost offering it promises. Different supply chains will be required for different 3-D products, he added. “Equipment costs are a big factor in our unit costs,” said Rich Rice, senior vice president of engineering and sales at ASE Group which is installing bonding/de-bonding, wafer thinning and other systems to handle the so-called middle steps of the 3-D process. “Even on the more traditional back-end we have a stiff cap ex burden when we start to ramp this capability up,” Rice said. A spokesman for Applied Materials noted the need for new 3-D systems comes while capital equipment makers are also trying to prepare systems for 450 mm wafers and the 20 and 14 nm nodes. Cisco’s Brillhart said he is concerned the many sometimes competing companies that need to come together to enable 3-D ICs find profitable ways to collaborate. “I’ve worked on too many programs where one of the partners in the supply chain became unprofitable and the technology went away,” he said. Moore’s Law more slowly The good news is experts see no fundamental barriers to scaling process technology down to at least 7 nm. The bad news is “as you go to smaller nodes the benefits of scaling are being eroded significantly,” said Iyer of IBM. The culprit is the lack of any new lithography techniques. Today’s 193 nm immersion lithography systems are being asked to create 22 and even 14 nm features. “This does not come free, the costs are becoming formidable,” Iyer said. “Complex patterning solutions are the cause of the angst we are having,” he added. Indeed costs of lithography will jump significantly at 20 nm and soar at 14 nm, said Kengeri of GlobalFoundries. The additional complexities and process and design costs are among the reasons the traditional two-year cadence between nodes is lengthening, he said. It took three extra quarters for the industry to qualify the 32/28 nm node and the ramp for the technology was a quarter longer than usual, Kengeri said. “Things are slowing down,” he added. According to a Merrill Lynch report, the cost of a single SoC project could bloat to $250 million at the 14 nm node, said Roawen Chen, vice president of manufacturing at Marvell Semiconductor. Masks costs alone will be about $7 million and the time from tapeout to first silicon could expand to six months, he said. “The bottom line is its becoming very expensive,” Chen said. The good news is one IBM researcher showed ways to make devices with as few as 25 atoms, opening the door to a 7 nm, process node. “Until we get to 7 nm or so there are no fundamental issues we see,” said Iyer.