联电能否在晶圆代工界翻身，就看IBM的了

联电(UMC)稍早前宣布，与 IBM 达成协议，将加快其 20nm 制程及 FinFET 3D 晶体管的发展，而此举也很可能让联电成为唯一一家在 20nm 节点提供 FinFET 组件的纯晶圆代工厂。 联电正在努力扭转局面。近年来，联电和主要竞争对手台积电(TSMC)的技术差距不断拉大，而Globalfoundries不久前也宣布销售额超越联电，将联电挤到了晶圆代工排名第三位。 台积电 (TSMC) 和 Globalfoundries 都可算在2014或2015年时，于 14nm 节点导入3D FinFET组件。部份先进代工客户如 Nvidia 则表示，他们希望代工厂能更快提供FinFET。因而部份业界人士猜测，台积电和GlobalFoundries很可能会改变他们的发展蓝图，提前纳入 FinFET。 Globalfoundries 发言人表示，该公司已经完成了完全耗尽型绝缘层上覆硅(SOI)技术的评估，预计2013年便可提供给客户使用，而早期采用的客户将可获得该技术提供的性 能优势。“我们和领先客户密切合作，以确保这项技术在成本、易于设计、微缩等方面都是最佳化的解决方案。” 英特尔 (Intel)已开始在22nm节点量产采用其FinFET组件(或称三闸极晶体管, tri-gate)的芯片。目前，许多领先的无晶圆厂公司们，都希望藉由该技术来改善功耗。(英特尔已公开表示该公司正在为少数几家规模较小的公司使用其 22nm 3D技术生产芯片。但也有传言指出，英特尔也正与其它数家公司就代工业务展开合作，其中还包括一些重量级的无晶圆厂芯片业者)。 在 20nm节点纳入FinFET将使联电在标准平面20nm制外，也有能力提供20nm制程的低功耗版本。无论是台积电或Globalfoundries， 都计划提供低功耗20nm制程。今年四月，台积电执行副总暨共同营运长蒋尚义曾表示，20nm的关键尺寸几乎没有足够空间来为不同闸极长度调整设计规则， 并提供不同版本的20nm制程了。 如果联电能及时提供 20nm FinFET 低功耗制程，就能与对手做出重大区隔。而这或许也是该公司夺回近年来不断被竞争对手所抢占市场的关键所在。 每个人都知道，功耗是芯片制造商和电子产业中几乎每个人都最关心的议题。若联电能在竞争对手都还没准备好时，就提供低功耗20nm FinFET制程，这对业界会是多么大的震撼？ 英特尔负责制程技术研发的资深院士Mark Bohr对今年四月《EE Times》报导台积电表示或许不打算提供低功耗20nm制程的报导所做出的反应，是认为芯片代工模式即将“崩溃”。Bohr的看法可能过于偏激了。但他 的出发点在于像美国高通这类无晶圆厂芯片业者，都会需要能尽可能降低芯片供耗的制程。 当然，目前有关联电的20nm FinFET仍然只是一个计划。即使获得IBM的技术，却也无法保证新制程的开发会一帆风顺。而联电本身也尚未对客户提供任何有关该技术的时间表。 然而，若一切依计划进行，则此举将大幅强化联电在代工领域的竞争力。 编译： Joy Teng 本文授权编译自EE Times，版权所有，谢绝转载 本文下一页：参考英文原文：UMC looks for boost with IBM license deal ，by Dylan McGrath

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{pagination} UMC looks for boost with IBM license deal Dylan McGrath United Microelectronics Corp.'s announcement Friday (June 29) that it has licensed from IBM technology to expedite the development of its 20-nm process, including FinFET transistors, likely means that UMC will be the only pure-play foundry to offer FinFETs at the 20-nm node. The effort appears to be an attempt by UMC to stem the tide of recent years. Rival Taiwan Semiconductor Manufacturing Co. (TSMC) has widened the technology gap with UMC as of late, and Globalfoundries Inc. recently surpassed UMC to claim the No. 2 position in foundry sales. Both TSMC and Globalfoundries are currently planning to introduce FinFETs—three-dimensional, fin-based multi-gate transistors—at the 14-nm node in 2014 or 2015. Some advanced foundry customers, including Nvidia Corp., have said they would like the foundries to offer FinFETs earlier. There is some speculation that TSMC and Globalfoundries may alter their roadmaps to incorporate FinFETs earlier. A spokesman for Globalfoundries said Friday that the company has been evaluating a fully depleted silicon-on-insulator technology offering in 2013 for early-adopter customers who may benefit from an additional performance boost. "We are in close discussion with leading customers to make sure this technology is the most optimum solution in terms of cost, ease of design, scaling and risk," the spokesman said. Intel Corp. is already producing chips with FinFETs—or what Intel calls tri-gate transistors—at the 22-nm node. Leading-edge fabless firms want the power consumption improvement promised by the technology. (Intel has publicly disclosed that it is making chips for a handful of smaller companies using its 22-nm 3-D process. Rumor has it that it is working on a foundry basis for several other companies, as well, including some fairly sizeable fabless chip vendors). The incorporation of FinFETs at 20-nm will enable UMC to offer a low-power version of its 20-nm process, in addition to a standard planar 20-nm process. Neither TSMC or Globalfoundries is planning to have a low-power 20-nm process. In April, Shang-yi Chiang, executive vice president and co-chief operating officer at TSMC, said critical dimensions are so tight at 20-nm that there isn't enough room for tweaking design rules to specify different gate lengths to enable different flavors of 20-nm processes. If UMC is able to offer a 20-nm low-power process with FinFETs in a timely fashion, it could be a major differentiator. It could be just what the company needs to recapture some of the ground it has given up to competitors in recent years. Everyone understands that power consumption is an issue of paramount concern to chip makers and just about everyone else in electronics today. How big of a deal will it be if UMC can offer a low-power 20-nm process with FinFETs at a time when competitors do not? Mark Bohr, the Senior Fellow at Intel who oversees the company's process technology development, reacted to the news that TSMC would not offer a low-power process at 20-nm by declaring to EE Times in April that the foundry model was "collapsing." Bohr's comments were self-serving and likely a little over the top. But his central point, that fabless chip vendors like Qualcomm Inc. need a process that will make its chips consume as little power as possible, has some merit. Of course, it should be said here that UMC's plan to offer FinFETs at 20-nm is, at this point, just a plan. Even with the IBM technology, there is no guarantee that devleoping the new process will go out without a hitch. And UMC itself has offered no timetable for when this technology will be available to customers. But if all goes according to plan, the move could well be enough to put UMC back in a place of greater relevance to leading edge foundry customers.