美光崛起！但够的着三星吗？

“市场占有率”在内存半导体市场中至关重要。“内存”可说是电子产业中最反复多变的领域之一；同时，价格、供给与需求的起起落落还使得亚洲、欧洲与北美等多家公司被逼至绝境，包括台湾的几家供货商，以及几年前由英飞凌科技(Infineon Technologies)独立而出的奇梦达(Qimonda)公司。 “规模”在此领域中也相当重要。一家公司规模越大，就越容易提供资本开支，能承受严峻的产品生命周期，并取得更高的市占率。这就是为什么收购尔必达公司(Elpida Memory)的这项交易决定对于美光公司(Micron Technology)来说格外重要。过去十多年来，这是美光公司第一次掌握了得以提升其市占率的大好机会，同时也增加其于另一波市场动荡后仍得以生存的机率。 根据市调机构 IHS 指出，这项收购协议同时也使得美光公司成为全球 DRAM 市场的第2大厂。IHS指出，美光公司将可占有大约四分之一的市场销售量，使其位居于领先韩国海力士半导体(Hynix Semiconductor Inc.)的位置。在该市场长期占主导地位的三星电子(Samsung Electronics)仍握有41%的最大市占率。 IHS公司负责 DRAM 与内存研究的资深首席分析师Mike Howard表示，收购尔必达对于美光公司目前在 DRAM 领域的地位具有重大的推升作用。 美光公司的市占率与DRAM制造产能可望提升将近一倍。再者，美光还取得了一些优越的行动DRAM技术，能够大幅地改善产品组合。25亿美元的收购价格合 理，而且也不至于对于美光公司的现金状况带来任何不利的影响。虽然这项交易至少还需要六个月的时间才完成收购，但IHS预期一旦整并行动展开后，很快地就 能完成转型与整合。 对于美光公司与其它主要的 DRAM 供货商而言，这项收购交易还带来了其它的好处。尔必达公司先前曾经宣布进入破产程序，此举大幅降低了厂房利用率与供应，因而使得DRAM价格趋于稳定。 IHS公司表示，在尔必达申请破产保护之前，“2011年在 DRAM 制造产能过剩，使得价格被压低并造成营收下降的情况下， DRAM 产业持续处于低迷。”因此，在这项收购交易完成后，美光预计将进一步减少尔必达的制造产能。 根据IHS公司表示：“由尔必达破产及随后被美光公司收购导致DRAM市场进一步趋于整并，将为DRAM带来新的稳定价格，从而有助于带动这个市场的复苏成长。” 预计今年全球 DRAM 产业营收将达到305亿美元，较2011年的296亿美元成长3.3%。尽管目前所看到的成长似乎很小，但相较于去年出现减少25%的惊人数字时，2012年的营收增加仍是令人庆幸的正面发展。 对于美光公司而言，收购尔必达虽然被为是一项积极的行动，但无疑地也将会对于OEM等小型厂商带来压力。像是南亚(Nanya)与华邦(Windbond) 等市占率低于5%的公司将会发现越来越难以和既有的厂商竞争。即使是海力士也很难全身而退。 DRAM 生产是一项高度资本密集的业务，供货商所在的位置越高，越容易为厂房及其它生产活动取得稳定的财务融资。 美光与尔必达的整并，还将使仍致力于解决投资人与金融业者等问题的海力士处于较不利的位置。但海力士可能因此让位于规模较小的竞争者，使其提高市占率吗？我想不太可能，因 为其它的竞争对手们目前的市占率都相当小，海力士不至于大幅改变其现有位置。而今，美光公司正处于一个更有利的市场位置，更有机会远远拉开其与海力士之间的距离。 想要迎头赶上三星公司，则又是另一个重大的行动。这家韩国巨擘──三星电子一向对于竞争对手采取各种施压策略行动绝 不手软，而且该公司还计划要在今年加码资本投资力度。无论美光公司目前的现金位置有多么稳健，在接下来的几年内，收购尔必达的协议都将为其带来现金债务， 因此，美光公司在现阶段仍无力负担或跟进。目前，美光公司将只能暂时居于市场第二的位置。 编译：Susan Hong 本文授权编译自EBN Online，版权所有，谢绝转载 本文下一页：参考英文原文：Micron Rising, But Can It Catch Samsung?，by Bolaji Ojo, Editor in Chief

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{pagination} Micron, Samsung seek hybrid memory spec Dylan McGrath SAN FRANCISCO—Micron Technology Inc. and South Korea's Samsung Electronics Co. Ltd. Thursday (Oct. 6) announced the formation of an open consortium around hybrid memory cube (HMC), a technology that brings DRAM memory and logic processes together into one package to offer potential power efficiency, bandwidth, density and scalability advantages over traditional DRAM. The goal of the Hybrid Memory Cube Consortium is to establish HMC as a new memory standard, according to Micron and Samsung. The consortium will begin meeting this month to develop a specification, which they expect to be released in 2012, the companies said. The group plans to share an early draft of an HMC interface specification with OEMs, ASIC developers and other firms at an early point for review, discussion and development, according to Scott Graham, general manager of DRAM marketing at Micron. Graham said additional HMC Consortium members would be announced later this year. "We fully expect that there will be additional developers comprised of OEMs and enablers who will essentially be guiding the development of this spec," Graham said. HMC relies on through-silicon-vias (TSVs)for three-dimensional stacked layers of memory with interconnect that increases performance and lowers power consumption. It also incorporates a logic layer that allows for multiple configurations for scalable bandwidth and the design flexibility for HMC to be implemented on multiple platforms, across many applications, according to Micron and Samsung. The technology also promises wide, high-speed local buses for data movement, advanced memory controller functions, DRAM control at memory, reduced memory controller complexity and increased efficiency, according to the companies. In February, Micron introduced HMC's ability to integrate DRAM and logic processes together in one package. The current HMC platform—demonstrated last month—has validated that it can run at 128 FB/s, providing significant bandwidth, density and energy efficiency improvements, according to Micron. Micron and Samsung believe that HMC has the potential to deliver significant improvements for applications ranging from networking and data center to consumer products such as media tablets and cards. HMC also represents a fundamental shift from current memory architectures, and driving its integration and adoption as an open standard will be a major undertaking, the companies said. Graham said the companies believe that HMC will have the greatest near-term impact in areas where performance and energy efficiency are most critical, such as networking and high-performance computing. But ultimately the companies believe the technology will be adopted into a wide-variety of wireless, medical, energy, transportation and security devices, he said. Graham described HMC as a response to significant challenges facing traditional DRAM, including the so-called "memory wall" created by the inability of DRAM vendors to march the performance improvements of processors. As a result, memory has become a significant bottleneck for system performance, he said. "The CPUs are capable of processing a lot more information than the DRAM is able to deliver," said Pablo Temprano, director of DRAM marketing at Samsung Semiconductor. In response to the disparity between the speed of processors and memory, engineers introduced a hierarchy of cache memory that is capable of running at processor clock speeds, according to Graham. But with the advent of multi-core, multi-threaded processors, the memory needs of computational algorithms sometimes exceed the capacity of the processor cache, he said. HMC offers the potential to alleviate this bottleneck, according to Graham and Temprano. A single HMC unit can provide more than 15 times the bandwidth of a DDR3 module and offer significant improvement in response to a random request stream, reducing system latency, they said.