FPGA开始进入SoC，下一代SoC将实现可编程

无晶圆厂FPGA供货商 Achronix Semiconductor Corp. 开始向芯片公司授权其FPGA技术，将业务范围扩展到了广大的 SoC市场。 Achronix 表示，将继续推出采用英特尔(Intel)制程制造的高性能 22nm FPGA ，但另一方面也将努力打入包括移动和消费应用在内的大量市场。 Achronix 的 22i Speedster FPGA 采用英特尔 22nm FinFET 制程，具备多种高速数据通信接口硬联机，包括10/40/100G以太网络MAC 、100Gb Interlaken 信道、PCI Express和 DDR3内存信道等。 本季，该公司还将发布一款具备60亿个晶体管的FPGA ── HD1000。Achronix 公司创办人暨主席 Lofton Holt 还透露， Achronix 将于2013年推出具备90亿个晶体管的FPGA，将采用相同的22nm FinFET制程。 不过，这些大容量FPGA都销定产量相对较小的高阶应用，如通信基础设施等，Holt说。随着越来越多SoC项目的上市时程落后，Holt认为，下一代SoC必然会是可编程的。 EFPGA FPGA向来是以单一封装组件提供板级的可编程特性。Holt表示，该公司已尝试将独立的逻辑和FPGA芯片整合在单一封装中，但不太成功。他认为，芯片级的整合会是下一个进化步骤。 Holt在说明Achronix 的IP产品时介绍了三款嵌入式FPGA (eFPGA)宏，它们带有100,000及100万之间的有效闸极，面积约2.1到19.2mm2，采用英特尔22nm FinFET制程。然而，Holt承认，目前许多与该公司接洽的客户都正在寻求自定义的FPGA架构(FPGA fabrics)。 Holt表示：“根据不同的性能和功耗要求，针对这些架构组成部份的芯片面积可减少高达40%。我们还计划在2013年支持先进的TSMC制程。” Holt表示，其IP业务的代工业者目前未定，但其所有的IP授权的相关客户均锁定TSMC。他接着表示，由英特尔制造的FPGA芯片也可能让该公司更快获得客户，将产品推向市场。 然而，目前有关其FPGA fabric的问题之一，是如何连接到芯片总线，以确保能为所有设计团队都可能尝试解决的中断来提供适合的额外资源。 Holt表示，Achronix已规划了三种可支持其FPGA技术的EDA流程。第一种是标准流程，工程师们可在RTL级对Achronix FPGA做编程。第二种是整合的SoC/FPGA设计流程，可支持在SoC内增加FPGA fabric并进行编程。第三种EDA流程将进一步扩展FPGA fabric中的可编程性，以支持可重配置功能。 Achronix 打算在2014年首次公开募股。为实现此一目标，Holt估计该公司将需要1亿美元的年销售额和70%以上的毛利率。“我要维持高利润，并进入手机市场。”他说。 本文授权编译自EE Times，版权所有，谢绝转载 编译： Joy Teng 参考英文原文：Achronix shifts gears, offers FPGA IP for SoCs ，by Peter Clarke

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{pagination} Achronix shifts gears, offers FPGA IP for SoCs Peter Clarke BRATISLAVA, Slovakia--Fabless FPGA vendor Achronix Semiconductor Corp. has jumped into the SoC market by offering to license its FPGA technology to chip companies. Achronix (Santa Clara, Calif.) will continue to market high-performance 22-nm FPGAs built by Intel Corp. on a foundry basis. But, in an effort to get into higher volume markets like mobile and consumer applications, Achronix will also license its FPGA fabric to serve as an insurance policy for SoC chip makers against a change in a standard or the need for a respin of the silicon, said John Lofton Holt, Achronix founder and chairman. Holt announced the addition of licensing to Achronix' business model to industry executives gathered here Thursday (Oct. 4) at the International Electronics Forum organized by Future Horizons. To date, Achronix has presented itself as a high-performance FPGA provider seeking to eclipse FPGA market leaders Altera Corp. and Xilinx Inc. Achronix drew attention when it switched foundries to go with Intel in an effort to claim the higher ground. Achronix' 22i Speedster FPGAs are manufactured using Intel's 22-nm FinFET manufacturing process and come with a variety of high-speed data communications interfaces hardwired. These include 10/40/100G Ethernet MACs, 100Gbit Interlaken channels, PCI Express and DDR3 memory channels. The HD1000 is a 6 billion transistor FPGA that will become available this quarter. Holt said Achronix would tape-out a 9 billion transistor FPGA in 2013 aimed at the same 22-nm FinFET manufacturing process. But while high-capacity FPGAs have their place, the space is reserved for relatively low-volume, high-end applications such as communications infrastructure, Holt said. As increasing numbers of SoC projects are delivered behind schedule and need multiple spins, Holt said. Silicon programmability is becoming a necessity for next-generation SoCs, Holt argued. eFPGA FPGA programmability has traditionally been supplied at the board level with a separate packaged device. Holt said attempts had been made to include separate logic and FPGA die in one package but with less success. Die-level integration is the next stage of that integration evolution, Holt argued. By way of an illustration of the Achronix IP offering Holt flashed up three embedded FPGA (eFPGA) macros with between 100,000 and 1 million effective gates and occupying between 2.1 and 19.2 square millimeters in Intel's 22-nm FinFET process. However, Holt admitted that most of the customers Achronix is engaged with today are looking for custom FPGA fabrics. In his presentation Holt said: "Depending on the performance and power requirements, the die area for some of these fabric components can be reduced by up to 40 percent. We are also planning to support advanced TSMC processes in 2013." Holt also admitted that while its IP business line will be foundry agnostic, all its present IP licensees are targeting TSMC. He added that Achronix could probably get customers to market faster with an Intel-produced chip as the FPGA fabric is fully characterized. "Intel foundry is not averse to this if the volumes are right," Holt said. However, doubts about the approach remain. One is how to connect the FPGA fabric into the on-chip bus to guarantee to provide suitable additional resources for all the disruptions the design team might be trying to insure against. Holt said Achronix now envisions three EDA design flows in support of its FPGA technology. The first is the standard flow that allows engineers to program Achronix FPGAs down to the RTL level, which Achronix has offered since 2008. The second is an integrated SoC/FPGA design flow to support the addition of FPGA fabric in SoCs and allow the fabric to be programmed. The third EDA flow will extend that FPGA fabric programmability to users to support functional reconfigurability. Achronix' current business plan of record is to conduct an initial public offering in 2014. To achieve that, Holt reckons the company will need $100 million of annual sales and 70-plus percent gross margins. "I want to stay high margin, to get into handsets," he said.