28nm SoC开发成本高出78%，盈利难度增大

根据Semico Research的报告显示，采用28nm制程的系统级芯片(SoC)设计成本较前一代40nm制程节点增加了78%，此外，软件成本增加的比重更高，提高约一倍以上。 Semicon估计，推出系统芯片所需的软件开发成本，目前已经远高于IC设计的成本了。 Semico Research指出，尽管在28nm节点的SoC设计成本比40nm节点时提高了78%以上，但用于编写与检查所需软件成本更上涨了102%。 软件所需负担的成本预计每年都将增加近一倍。Semico预测，在10nm芯片制程节点以前，每年用于SoC软件开发的成本年复合成长率(CAGR)约79%。整合分离式IP模组于当代SoC中的成本年复合成长率(CAGR)也达到了77.2%。 对于芯片开发商而言，好消息是Semico公司预期芯片设计成本的增加将较缓和。20nm节点时的SoC设计成本预计将较28nm节点时增加48%，到了14nm时将增加31%，而在10nm节点时增加约35%。 由于软件负担以及整合多方IP核心的成本提高，预计在突破新制程节点时的先进多核心设计将达到最高成本。Semico表示，同一制程节点时所衍生的SoC设计成本都只是首次开发成本的一小部份。 同时，专为某一既有节点建置的新设计，其成本将随着时间的进展逐渐大幅降低。在14nm节点实现商用化以前，45nm节点高性能多核心SoC设计成本的CAGR为-12.7%。 Semico并估计以20nm制造的芯片售价约20美元，因而必须达到920万片的出货量，实现超过1.8亿美元的营收，方能取得盈亏平衡。 编译：Susan Hong 参考原文：28-nm SoC development costs doubled over 40-nm，by Peter Clarke

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{pagination} The cost of designing system-on-chip silicon at 28-nm went up by 78 percent over the previous node, but the software cost was larger and more than doubled, says Semico Research. Semico reckons the cost of developing the software that it is necessary to ship with system chips is now greater than the cost of the IC design. While the cost of SoC design at the 28-nm node is 78 percent more than it was at the 40-nm node the cost of writing and checking the necessary software went up by 102 percent, the market researcher claims. And the software burden will increase close to doubling in cost every year. Semico predicts a compound annual growth rate for SoC software development of 79 percent through to the arrival of the 10-nm chip manufacturing node. The cost to integrate discrete IP blocks used in contemporary SoCs is also rising showing a CAGR of 77.2 percent, Semico said. The good news for chip developers is that Semico forecasts that the growth of chip design cost will be lower. Semico said it expects SoC design costs to increase 48 percent at the 20-nm node compared with the 28-nm node. They are expected to increase by a further 31 percent at the 14-nm node and by 35 percent at the 10-nm node. Because of the high software burden and the cost of integrating IP cores from multiple sources the highest costs are seen in advanced multicore designs that break in a new process node. Derivative SoC designs at the same process node are a fraction of the cost of those first-time designs Semico said. At the same time novel designs that are designed for an established manufacturing node will show a marked reduction in cost over time. The costs for an advanced performance multicore SoC design, continuously done at the 45-nm node will experience a negative CAGR of 12.7 percent by the time the 14-nm process node becomes commercially available. Semico estimates that an made in 20-nm silicon that sells for $20 must ship 9.2 million units and achieve more than $180 million in revenue to breakeven.

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